Jens Leenstra

According to our database, Jens Leenstra authored at least 22 papers between 1989 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2015

Advanced features in IBM POWER8 systems.

Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block

IBM J. Res. Dev., 2015

IBM POWER8 processor core microarchitecture.

Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler

IBM J. Res. Dev., 2015

2014

POWER8 design methodology innovations for improving productivity and reducing power.

Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

DB2 with BLU Acceleration: So Much More than Just a Column Store.

Vijayshankar Raman, Gopi K. Attaluri, Ronald Barber, Naresh Chainani, David Kalmuk, Vincent KulandaiSamy, Jens Leenstra, Sam Lightstone, Shaorong Liu, Guy M. Lohman, Tim Malkemus, René Müller, Ippokratis Pandis, Berni Schiefer, David Sharpe, Richard Sidle, Adam J. Storm, Liping Zhang

Proc. VLDB Endow., 2013

2011

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban

IEEE J. Solid State Circuits, 2011

2008

Scan chain clustering for test power reduction.

Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding

Proceedings of the 45th Design Automation Conference, 2008

2007

Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process.

Joachim Fenkes, Tobias Gemmeke, Jens Leenstra

J. Low Power Electron., 2007

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata

IBM J. Res. Dev., 2007

IBM POWER6 accelerators: VMX and DFU.

Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough

IBM J. Res. Dev., 2007

Scan Test Planning for Power Reduction.

Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra

Proceedings of the 44th Design Automation Conference, 2007

2006

The microarchitecture of the synergistic processor for a cell processor.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata

IEEE J. Solid State Circuits, 2006

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.

Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

The vector fixed point unit of the synergistic processor element of the cell architecture processor.

Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2001

A 1.8-GHz instruction window buffer for an out-of-order microprocessor core.

Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel

IEEE J. Solid State Circuits, 2001

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.

Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Custom circuit design as a driver of microprocessor performance.

David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel

IBM J. Res. Dev., 2000

1997

Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.

Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile

Proceedings of the 34st Conference on Design Automation, 1997

1991

Hierarchical Test Program Development for Scan Testable Circuits.

Jens Leenstra, Lambert Spaanenburg

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Hierarchical test assembly for macro based VLSI design.

Jens Leenstra, Lambert Spaanenburg

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

On structured gate forest VLSI design.

Gerhard Roos, Jens Leenstra, Thomas Schwederski, Lambert Spaanenburg, Bernd Höfflinger

Microprocessing and Microprogramming, 1989

On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems.

Jens Leenstra, Lambert Spaanenburg

Proceedings of the Proceedings International Test Conference 1989, 1989

Issues in the test of artificial neural networks.

Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989