Jens Leenstra
According to our database1,
Jens Leenstra
authored at least 22 papers
between 1989 and 2015.
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Bibliography
2015
2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proc. VLDB Endow., 2013
2011
IEEE J. Solid State Circuits, 2011
2008
Proceedings of the 45th Design Automation Conference, 2008
2007
J. Low Power Electron., 2007
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM J. Res. Dev., 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
2005
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2001
IEEE J. Solid State Circuits, 2001
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
2000
IBM J. Res. Dev., 2000
1997
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.
Proceedings of the 34st Conference on Design Automation, 1997
1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
1989
Proceedings of the Proceedings International Test Conference 1989, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989