Jens Kargaard Madsen

According to our database1, Jens Kargaard Madsen authored at least 24 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs.
IEEE Trans. Emerg. Top. Comput., 2019

Low-Power High-Input-Impedance EEG Signal Acquisition SoC With Fully Integrated IA and Signal-Specific ADC for Wearable Applications.
IEEE Trans. Biomed. Circuits Syst., 2019

A low-power, low-noise, high-accurate epileptic-seizure detection system for wearable applications.
Microelectron. J., 2019

Spin-Orbit-Torque-based Devices, Circuits and Architectures.
CoRR, 2019

2018
A Low-Power High-Speed Spintronics-Based Neuromorphic Computing System Using Real-Time Tracking Method.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.
Int. J. Circuit Theory Appl., 2017

Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

An energy efficient neuromorphic computing system using real time sensing method.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A low-power analog front-end neural acquisition design for seizure detection.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Low-power comparator in 65-nm CMOS with reduced delay time.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

STT-RAM write energy consumption reduction by differential write termination method.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology.
Microelectron. J., 2014

8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Improved read and write margins using a novel 8T-SRAM cell.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Robust subthreshold 7T-SRAM cell for low-power applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2012
Flip-flop design using novel pulse generation technique.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

1996
A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI.
IEEE J. Solid State Circuits, 1996

1995
A High-Speed Interconnect Network Using Ternary Logic.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995


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