Jennifer Pham

According to our database, Jennifer Pham authored at least 4 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.

Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.

Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2011

An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology.

Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008

A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate.

Jennifer Pham, Anthony Chan Carusone

IEEE Trans. Circuits Syst. II Express Briefs, 2008