Jennifer Dworak

According to our database¹, Jennifer Dworak authored at least 71 papers between 1999 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Dual Use Circuitry for Early Failure Warning and Test.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.

[BibT_eX]

[DOI]

J. Electron. Test., April, 2023

Harvesting Wasted Clock Cycles for Efficient Online Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

2021

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

2020

A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks.

[BibT_eX]

[DOI]

David Brauchler

Jennifer Dworak

Proceedings of the IEEE International Test Conference, 2020

2019

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Innovate Practices on CyberSecurity of Hardware Semiconductor Devices.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Test Architecture for Fine Grained Capture Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Efficient parallel testing: A configurable and scalable broadcast network design using IJTAG.

[BibT_eX]

[DOI]

Saurabh Gupta

Jae Wu

Jennifer Dworak

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

One more time! Increasing fault detection with scan shift capture.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE North Atlantic Test Workshop, 2018

IJTAG Integrity Checking with Chained Hashing.

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

Proceedings of the IEEE International Test Conference, 2018

Can Soft Errors be Handled Securely?

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Mitigating simple power analysis attacks on LSIB key logic.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Detecting a trojan die in 3D stacked integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Increasing IJTAG bandwidth and managing security through parallel locking-SIBs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

Systematic Test Generation for Secure Hardware Supported Virtualization.

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

Proceedings of the 15th IEEE Intl Conf on Dependable, 2017

2016

Using Existing Reconfigurable Logic in 3D Die Stacks for Test.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor.

[BibT_eX]

[DOI]

Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Echeloned IJTAG data protection.

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

James George Dunham

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

2015

Repairing a 3-D Die-Stack Using Available Programmable Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard.

[BibT_eX]

[DOI]

Jennifer Dworak

Al Crouch

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices.

[BibT_eX]

[DOI]

Jennifer Dworak

Ping Gui

Qutaiba Khasawneh

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation.

[BibT_eX]

[DOI]

Senwen Kan

Marco Ottavi

Jennifer Dworak

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Special session 4A: Elevator talks.

[BibT_eX]

[DOI]

Jennifer Dworak

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

When Optimized N-Detect Test Sets are Biased: An Investigation of Cell-Aware-Type Faults and N-Detect Stuck-At ATPG.

[BibT_eX]

[DOI]

Fanchen Zhang

Micah Thornton

Jennifer Dworak

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Board security enhancement using new locking SIB-based architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Triggering Trojans in SRAM circuits with X-propagation.

[BibT_eX]

[DOI]

Senwen Kan

Jennifer Dworak

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects.

[BibT_eX]

[DOI]

Yiwen Shi

Jennifer Dworak

J. Electron. Test., 2013

FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Special session 4B: Elevator talks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Don't forget to lock your SIB: Hiding instruments using P16871.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Ternary Logic Network Justification Using Transfer Matrices.

[BibT_eX]

[DOI]

Mitchell A. Thornton

Jennifer Dworak

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Built-in Self-Repair in a 3D die stack using programmable logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Using implications to choose tests through suspect fault identification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Enhancing online error detection through area-efficient multi-site implications.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Partial state monitoring for fault detection estimation.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

2010

A Cost Effective Approach for Online Error Detection Using Invariant Relationships.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Reducing Scan Shift Activity at RTL.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects.

[BibT_eX]

[DOI]

Yiwen Shi

Wan-Chan Hu

Jennifer Dworak

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Improving the testability and reliability of sequential circuits with invariant logic.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

NIM- a noise index model to estimate delay discrepancies between silicon and simulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Compacting test vector sets via strategic use of implications.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Detecting errors using multi-cycle invariance information.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Reducing Scan Shift Power at RTL.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Using Implications for Online Error Detection.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization.

[BibT_eX]

[DOI]

Yiwen Shi

Kellie DiPalma

Jennifer Dworak

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting.

[BibT_eX]

[DOI]

Jennifer Dworak

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Which defects are most critical? optimizing test sets to minimize failures due to test escapes.

[BibT_eX]

[DOI]

Jennifer Dworak

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects.

[BibT_eX]

[DOI]

Jennifer Dworak

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

2004

Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects.

[BibT_eX]

[DOI]

Jennifer Dworak

James Wingfield

M. Ray Mercer

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Function-Based Dynamic Compaction and its Impact on Test Set Sizes.

[BibT_eX]

[DOI]

James Wingfield

Jennifer Dworak

M. Ray Mercer

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Enhancing test efficiency for delay fault testing using multiple-clocked schemes.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Defect-Oriented Testing and Defective-Part-Level Prediction.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

2000

Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Jennifer Dworak

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...