Jeng-Liang Tsai

According to our database, Jeng-Liang Tsai authored at least 13 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Temperature-Aware Placement for SOCs.

Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar

Proc. IEEE, 2006

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method.

Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.

Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Yield-Driven, False-Path-Aware Clock Skew Scheduling.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

IEEE Des. Test Comput., 2005

False Path and Clock Scheduling Based Yield-Aware Gate Sizing.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis.

Jeng-Liang Tsai, Lizheng Zhang

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.

Jeng-Liang Tsai, Charlie Chung-Ping Chen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.

Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Sensitivity guided net weighting for placement driven synthesis.

Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen

Proceedings of the 2004 International Symposium on Physical Design, 2004

A yield improvement methodology using pre- and post-silicon statistical clock scheduling.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

HiSIM: hierarchical interconnect-centric circuit simulator.

Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Thermal and Power Integrity Based Power/Ground Networks Optimization.

Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen

Proceedings of the 2004 Design, 2004

2003

Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.

Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen

Proceedings of the 2003 International Symposium on Physical Design, 2003