An Efficient Timing Model for CMOS Combinational Logic Gates. - Chung-Yu Wu; Jen-Sheng Hwang; Chin Chang; Ching-Chu Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Multi-project chip service for university and industry in Taiwan. - Jen-Sheng Hwang (ASP-DAC, 1997)

ROM/PROM/EPROM. - Jen-Sheng Hwang (The VLSI Handbook, 1999)