Jen-Chieh Yeh

According to our database, Jen-Chieh Yeh authored at least 37 papers between 2001 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.

Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Multi-core system performance prediction and analysis at the ESL.

Jen-Chieh Yeh, Chi-Hung Lin, Chun-Nan Liu

Int. J. Comput. Sci. Eng., 2014

Full system simulation framework for integrated CPU/GPU architecture.

Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system.

Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang

Proceedings of the IEEE International Conference on Acoustics, 2014

2013

Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus.

Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh

ACM Trans. Embed. Comput. Syst., 2013

A Cycle Count Accurate TLM bus modeling approach.

Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.

Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.

Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL.

Mao-Yin Wang, Jen-Chieh Yeh

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.

Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011

System power analysis with DVFS on ESL virtual platform.

Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology.

Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng

Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.

Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh

Proceedings of the 48th Design Automation Conference, 2011

System-level design exploration for 3-D stacked memory architectures.

Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

An accurate system architecture refinement methodology with mixed abstraction-level virtual platform.

Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang

Proceedings of the Design, Automation and Test in Europe, 2010

PAC duo system power estimation at ESL.

Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

System Performance Analyses on PAC Duo ESL Virtual Platform.

Zhe-Mao Hsu, I-Yao Chuang, Wen-Chien Su, Jen-Chieh Yeh, Jen-Kuei Yang, Shau-Yin Tseng

Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

Full System Simulation and Verification Framework.

Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao

Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2008

A Systematic Approach to Memory Test Time Reduction.

Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo

IEEE Des. Test Comput., 2008

2007

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.

Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Raisin: Redundancy Analysis Algorithm Simulation.

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu

IEEE Des. Test Comput., 2007

SDRAM Delay Fault Modeling and Performance Testing.

Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

Fault-Pattern Oriented Defect Diagnosis for Flash Memory.

Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

An Enhanced EDAC Methodology for Low Power PSRAM.

Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin

Proceedings of the 2006 IEEE International Test Conference, 2006

A network security processor design based on an integrated SOC design and test platform.

Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang

Proceedings of the 43rd Design Automation Conference, 2006

2005

A built-in self-repair design for RAMs with 2-D redundancy.

Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2005

Flash Memory Built-In Self-Diagnosis with Test Mode Control.

Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A systematic approach to reducing semiconductor memory test time in mass production.

Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Flash Memory Die Sort by a Sample Classification Method.

Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

On Test and Diagnostics of Flash Memories.

Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.

Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.

Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Diagonal Test and Diagnostic Schemes for Flash Memorie.

Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.

Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.

Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001