Jen-Chieh Liu

Orcid: 0000-0002-7045-6586

According to our database¹, Jen-Chieh Liu authored at least 28 papers between 2006 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2024

A Programmable DLL-based Delay Chain.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

A Low-power PLL with a Standby Mode.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

2023

A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., April, 2023

2021

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator.

[BibT_eX]

[DOI]

Jen-Chieh Liu

Yu-Ping Li

IEEE Access, 2021

2018

A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution.

[BibT_eX]

[DOI]

Jen-Chieh Liu

Chao-Jen Huang

Pei-Ying Lee

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.

[BibT_eX]

[DOI]

Jen-Chieh Liu

Tzu-Yun Wu

Tuo-Hung Hou

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Low supply voltage and multiphase all-digital crystal-less clock generator.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2018

2017

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.

[BibT_eX]

[DOI]

Yo-Hao Tu

Jen-Chieh Liu

Kuo-Hsing Cheng

IEICE Trans. Electron., 2016

A Low Power Pulse Generator for Test Platform Applications.

[BibT_eX]

[DOI]

Jen-Chieh Liu

Pei-Ying Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

A chaotically injected timing technique for ring-based oscillators.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Cheng-Liang Hung

Cihun-Siyong Alex Gong

Jen-Chieh Liu

Bo-Qian Jiang

Shi-Yang Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A radio-controlled receiver for clocks/watches and alarm applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 64-MHz∼640-MHz 64-phase clock generator.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2012

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator.

[BibT_eX]

[DOI]

Kuo-Hsing Cheng

Jen-Chieh Liu

Hong-Yi Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Auto-calibration techniques in built-in jitter measurement circuit.

[BibT_eX]

[DOI]

Chih-Ping Cheng

Jen-Chieh Liu

Kuo-Hsing Cheng

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

All digital phase-locked loop using active inductor oscillator and novel locking algorithm.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

A loading effect insensitive and high precision clock synchronization circuit.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

0.5V 160-MHz 260uW all digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2007

All-Digital PLL Using Pulse-Based DCO.

[BibT_eX]

[DOI]

Hong-Yi Huang

Jen-Chieh Liu

Kuo-Hsing Cheng

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.

[BibT_eX]

[DOI]

Hong-Yi Huang

Bo-Ruei Wang

Jen-Chieh Liu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Jen-Chieh Liu

Timeline

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On csauthors.net:

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