Jelena Trajkovic

Orcid: 0000-0001-5361-205X

According to our database1, Jelena Trajkovic authored at least 24 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Value Prediction for Spatiotemporal Gait Data Using Deep Learning.
CoRR, 2024

2023
Instructor Perspectives on Prerequisite Courses in Computing.
Proceedings of the 54th ACM Technical Symposium on Computer Science Education, Volume 1, 2023

2022
Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC.
ACM Trans. Embed. Comput. Syst., 2022

2018
Comparative study and prediction modeling of photonic ring Network on Chip architectures.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2016
Photonic integrated circuits: A study on process variations.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A Clustered GALS NoC Architecture with Communication-Aware Mapping.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

On improving the range of inductive proximity sensors for avionic applications.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Optical crossbars on chip, a comparative study based on worst-case losses.
Concurr. Comput. Pract. Exp., 2014

Fast and accurate implementation of Canny edge detector on embedded many-core platform.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Chameleon: Channel efficient Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Quota setting router architecture for quality of service in GALS NoC.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Potential and pitfalls of silicon photonics computing and interconnect.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Automated Generation of Custom Processor Core from C Code.
J. Electr. Comput. Eng., 2012

2011
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett., 2010

Early performance-cost estimation of application-specific data path pipelining.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2008
Improving SDRAM access energy efficiency for low-power embedded systems.
ACM Trans. Embed. Comput. Syst., 2008

Custom Processor Core Construction from C Code.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

2007
Automatic Data Path Generation from C code for Custom Processors.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

2006
A Graph Based Algorithm for Data Path Optimization in Custom Processors.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006


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