Jei-Hwan Yoo

According to our database¹, Jei-Hwan Yoo authored at least 10 papers between 1996 and 2012.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2012

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

8Gb 3D DDR3 DRAM using through-silicon-via technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2003

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

1997

Low-voltage, high-speed circuit designs for gigabit DRAMs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

An efficient statistical analysis methodology and its application to high-density DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Jei-Hwan Yoo

Timeline

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On csauthors.net:

Bibliography

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