Jeffrey Tyhach

According to our database, Jeffrey Tyhach authored at least 3 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2015

Arria™ 10 device architecture.

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2005

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.

Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan

IEEE J. Solid State Circuits, 2005

2004

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.

Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004