Jeffrey L. Burns

According to our database, Jeffrey L. Burns authored at least 20 papers between 1986 and 2017.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of two.

2017

Panel discussions: "Cool chips for the next decade".

Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash

Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2011

Technology trends and implications on SoC design.

Jeffrey L. Burns

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2004

Resonant clocking using distributed parasitic capacitance.

Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown

IEEE J. Solid State Circuits, 2004

Analysis and Optimization of Enhanced MTCMOS Scheme.

Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Efficient techniques for gate leakage estimation.

Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A semi-custom voltage-island technique and its application to high-speed serial links.

Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Leakage and leakage sensitivity computation for combinational circuits.

Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.

Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.

Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies.

Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown

Proceedings of the ESSCIRC 2003, 2003

2002

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.

Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns

IEEE J. Solid State Circuits, 2002

1999

Performance Driven Synthesis for Pass-Transistor Logic.

Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

C5M-a control-logic layout synthesis system for high-performance microprocessors.

Jeffrey L. Burns, Jack A. Feldman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Designing for a gigahertz [guTS integer processor].

H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi

IEEE Micro, 1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.

Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

IEEE J. Solid State Circuits, 1998

Design methodology for a 1.0 GHz microprocessor.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Area-oriented synthesis for pass-transistor logic.

Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1994

The Effect of Wire Length Minimization on Yield.

Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1988

Techniques for multilayer channel routing.

Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986

Chameleon: a new multi-layer channel router.

Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986