Jeffrey J. Cook

According to our database1, Jeffrey J. Cook authored at least 15 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
WRPN: Wide Reduced-Precision Networks.
Proceedings of the 6th International Conference on Learning Representations, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
WRPN: Training and Inference using Wide Reduced-Precision Networks.
CoRR, 2017

2011
Scaling short read de novo DNA sequence assembly to gigabase genomes
PhD thesis, 2011

2009
Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Blueshift: Designing processors for timing speculation from the ground up.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
A characterization of instruction-level error derating and its implications for error detection.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor.
Microprocess. Microsystems, 2007

2005
Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
A reconfigurable unit for a clustered programmable-reconfigurable processor.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Mapping computation kernels to clustered programmable-reconfigurable processors.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002
Clustered programmable-reconfigurable processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

The Design of the Amalgam Reconfigurable Cluster.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002


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