Jeffrey A. Davis
Orcid: 0000-0003-4537-4084Affiliations:
- Georgia Institute of Technology, Atlanta GA, USA
According to our database1,
Jeffrey A. Davis
authored at least 30 papers
between 1998 and 2021.
Collaborative distances:
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Bibliography
2021
Multidimensional analysis of excitonic spectra of monolayers of tungsten disulphide: toward computer-aided identification of structural and environmental perturbations of 2D materials.
Mach. Learn. Sci. Technol., 2021
2008
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2007
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
A priori prediction of tightly clustered connections based on heuristic classification trees.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004
2003
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
A physical model for the transient response of capacitively loaded distributed rlc interconnects.
Proceedings of the 39th Design Automation Conference, 2002
2001
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
2000
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE J. Solid State Circuits, 2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1998
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998