Jeff Sondeen

According to our database1, Jeff Sondeen authored at least 10 papers between 2002 and 2009.

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Bibliography

2009
Multicast routing with dynamic packet fragmentation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Floating-point division and square root implementation using a Taylor-series expansion algorithm.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.
J. VLSI Signal Process., 2005

An area-efficient and protected network interface for processing-in-memory systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A 0.18 µm implementation of a floating-point unit for a processing-in-memory system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An area-efficient standard-cell floating-point unit design for a processing-in-memory system.
Proceedings of the ESSCIRC 2003, 2003

2002
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002


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