Jeferson Santiago da Silva

According to our database, Jeferson Santiago da Silva authored at least 9 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Design Principles for Packet Deparsers on FPGAs.

Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020

Bridging the Gap: FPGAs as Programmable Switches.

Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois

Proceedings of the 21st IEEE International Conference on High Performance Switching and Routing, 2020

Unleashing the Power of FPGAs as Programmable Switches.

Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design.

Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Extern Objects in P4: an ROHC Header Compression Scheme Case Study.

Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois

Proceedings of the 4th IEEE Conference on Network Softwarization and Workshops, 2018

One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing.

Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala

Proceedings of the 2018 IEEE 26th International Conference on Network Protocols, 2018

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.

Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2016

Extern Objects in P4: an ROHC Compression Case Study.

Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois

CoRR, 2016

2015

Area-oriented iterative method for Design Space Exploration with High-Level Synthesis.

Jeferson Santiago da Silva, Sergio Bampi

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015