Jeanine E. Cook
According to our database1,
Jeanine E. Cook
authored at least 44 papers
between 2002 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.
IEEE Trans. Computers, 2022
2021
ACM Trans. Archit. Code Optim., 2021
J. Comput. Inf. Sci. Eng., 2021
2020
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams.
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
2019
Fine-Grained Analysis of Communication Similarity between Real and Proxy Applications.
Proceedings of the 2019 IEEE/ACM Performance Modeling, 2019
Proceedings of the 2019 IEEE International Conference on Cluster Computing, 2019
2018
A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC.
J. Supercomput., 2018
ACM Trans. Archit. Code Optim., 2018
Exploring and Quantifying How Communication Behaviors in Proxies Relate to Real Applications.
Proceedings of the 2018 IEEE/ACM Performance Modeling, 2018
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
A Methodology for Characterizing the Correspondence Between Real and Proxy Applications.
Proceedings of the IEEE International Conference on Cluster Computing, 2018
2017
PeaPaw: Performance and Energy-Aware Partitioning of Workload on Heterogeneous Platforms.
ACM Trans. Design Autom. Electr. Syst., 2017
DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs.
CoRR, 2017
Proceedings of the 2017 IEEE SmartWorld, 2017
DAdHTM: Low overhead dynamically adaptive hardware transactional memory for large graphs a scalability study.
Proceedings of the 2017 IEEE SmartWorld, 2017
Performance and Power Characteristics and Optimizations of Hybrid MPI/OpenMP LULESH Miniapps under Various Workloads.
Proceedings of the 5th International Workshop on Energy Efficient Supercomputing, 2017
Proceedings of the International Symposium on Memory Systems, 2017
DyAdHyTM: a low overhead dynamically adaptive hybrid transactional memory with application to large graphs.
Proceedings of the International Symposium on Memory Systems, 2017
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017
StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017
2016
Computer, 2016
Using Intrinsic Performance Counters to Assess Efficiency in Task-Based Parallel Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS).
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015
2014
Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2014
Accurate statistical performance modeling and validation of out-of-order processors using Monte Carlo methods.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014
2013
Proceedings of the 5th International Workshop on Software Engineering for Computational Science and Engineering, 2013
2012
Proceedings of the 2012 SC Companion: High Performance Computing, 2012
2011
SIGMETRICS Perform. Evaluation Rev., 2011
2010
Extending the Monte Carlo Processor Modeling Technique: Statistical Performance Models of the Niagara 2 Processor.
Proceedings of the 39th International Conference on Parallel Processing, 2010
2007
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007
2006
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006
2005
Proceedings of the 13th International Symposium on Modeling, 2005
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
2002
Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2002