Jean-Philippe Diguet
Orcid: 0000-0003-0728-6040
According to our database1,
Jean-Philippe Diguet
authored at least 191 papers
between 1996 and 2024.
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on dl.acm.org
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Bibliography
2024
CoRR, 2024
Applying a Systematic Approach to Design Human-Robot Cooperation in Dynamic Environments.
Proceedings of the 21st International Conference on Informatics in Control, 2024
Discretization Strategies for Improved Health State Labeling in Multivariable Predictive Maintenance Systems.
Proceedings of the 13th International Conference on Data Science, 2024
2023
IEEE Trans Autom. Sci. Eng., October, 2023
2022
J. Signal Process. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
J. Intell. Robotic Syst., 2022
Ann. des Télécommunications, 2022
Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning.
Proceedings of the Advances in System-Integrated Intelligence, 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
Mitigating Transceiver and Token Controller Permanent Faults in Wireless Network-on-Chip.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Proceedings of the 2022 International Wireless Communications and Mobile Computing, 2022
Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the Advanced Information Networking and Applications, 2022
2021
IEEE Trans. Parallel Distributed Syst., 2021
IEEE Trans. Emerg. Top. Comput., 2021
Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors.
ACM Trans. Embed. Comput. Syst., 2021
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Sensors, 2021
ECTM: A network-on-chip communication model to combine task and message schedulability analysis.
J. Syst. Archit., 2021
Design and Comparison of Reward Functions in Reinforcement Learning for Energy Management of Sensor Nodes.
CoRR, 2021
A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
On Cache Limits for Dataflow Applications and Related Efficient Memory Management Strategies.
Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV.
Proceedings of the International Workshop on Rapid System Prototyping, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Comparison of Market-based and DQN methods for Multi-Robot processing Task Allocation (MRpTA).
Proceedings of the Fourth IEEE International Conference on Robotic Computing, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
J. Low Power Electron., 2019
Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems.
ACM J. Emerg. Technol. Comput. Syst., 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
CDMA-based multiple multicast communications on WiNOC for efficient parallel computing.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the 16th International Symposium on Wireless Communication Systems, 2019
A Case Study of Primary User Arrival Prediction Using the Energy Detector and the Hidden Markov Model in Cognitive Radio Networks.
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Integrating Operators' Preferences into Decisions of Unmanned Aerial Vehicles: Multi-layer Decision Engine and Incremental Preference Elicitation.
Proceedings of the Algorithmic Decision Theory - 6th International Conference, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Context/Resource-Aware Mission Planning Based on BNs and Concurrent MDPs for Autonomous UAVs.
Sensors, 2018
Towards Dynamically Reconfigurable SoCs (DRSoCs) in industrial automation: State of the art, challenges and opportunities.
Microprocess. Microsystems, 2018
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip.
J. Parallel Distributed Comput., 2018
Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Accurate Channel Models for Realistic Design Space Exploration of Future Wireless NoCs.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures.
Proceedings of the 2018 IEEE International Conference on Autonomic Computing, 2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.
Proceedings of the 55th Annual Design Automation Conference, 2018
Discrete and Logico-Numerical Control for Dynamic Partial Reconfigurable FPGA-Based Embedded Systems: A Case Study.
Proceedings of the IEEE Conference on Control Technology and Applications, 2018
2017
J. Signal Process. Syst., 2017
DTFM: a flexible model for schedulability analysis of real-time applications on NoC-based architectures.
SIGBED Rev., 2017
Microprocess. Microsystems, 2017
Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform.
Int. J. Reconfigurable Comput., 2017
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Signal Process., 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
Proceedings of the 6th Mediterranean Conference on Embedded Computing, 2017
Proceedings of the 29th International Conference on Microelectronics, 2017
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017
2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016
TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA.
ACM Trans. Embed. Comput. Syst., 2016
Model-Based Design of Correct Controllers for Dynamically Reconfigurable Architectures.
ACM Trans. Embed. Comput. Syst., 2016
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithms.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., 2015
Dedicated object processor for mobile augmented reality - sailor assistance case study.
EURASIP J. Embed. Syst., 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the 14th International Conference on Information Processing in Sensor Networks, 2015
Proceedings of the 2015 IEEE Conference on Prognostics and Health Management, 2015
Proceedings of the Distributed Computing and Internet Technology, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015
Bayesian network-based framework for the design of reconfigurable health management monitors.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling.
ACM Trans. Reconfigurable Technol. Syst., 2014
Proceedings of the 6th International Conference of Soft Computing and Pattern Recognition, 2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Extensible Global Model Management with Meta-model Subsets and Model Synchronization.
Proceedings of the 2nd International Workshop on The Globalization of Modeling Languages co-located with ACM/IEEE 17th International Conference on Model Driven Engineering Languages and Systems, 2014
Synchronization of Models of Rich Languages with Triple Graph Grammars: An Experience Report.
Proceedings of the Theory and Practice of Model Transformations, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
Int. J. Reconfigurable Comput., 2013
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Embedded System Architecture for Mobile Augmented Reality - Sailor Assistance Case Study.
Proceedings of the PECCS 2013, 2013
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Autonomic Management of Dynamically Partially Reconfigurable FPGA Architectures Using Discrete Control.
Proceedings of the 10th International Conference on Autonomic Computing, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Scalable NoC-based architecture of neural coding for new efficient associative memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
A contribution to the reduction of the dynamic power dissipation in the turbo decoder.
Ann. des Télécommunications, 2012
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
Proceedings of the 2012 International Conference on Multimedia Computing and Systems, 2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
Closed-loop-based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study.
ACM Trans. Embed. Comput. Syst., 2011
Asymmetric cache coherency: Improving multicore performance for non-uniform workloads.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Distributed Security for Communications and Memories in a Multiprocessor Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010
Predictibility of inter-component latency in a software communications architecture operating environment.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Microprocess. Microsystems, 2009
Energy and Power Consumption Estimation for Embedded Applications and Operating Systems.
J. Low Power Electron., 2009
Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Model Driven High-Level Power Estimation of Embedded Operating Systems Communication Services.
Proceedings of the International Conference on Embedded Software and Systems, 2009
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
A co-design approach for embedded system modeling and code generation with UML and MARTE.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the IEEE Conference on Automation Science and Engineering, 2009
Proceedings of the Architecture of Computing Systems, 2009
2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2008
EURASIP J. Embed. Syst., 2008
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Embed. Syst., 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the Languages for Embedded Systems and their Applications, 2008
Specification and OS-based implementation of self-adaptive, hardware/software embedded systems.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Efficient space-time noc path allocation based on mutual exclusion and pre-reservation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the FPL 2007, 2007
High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
A Code Compression Method with Confidentiality and Integrity Checking.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter.
J. VLSI Signal Process., 2006
Microelectron. J., 2006
Microprocess. Microsystems, 2006
EURASIP J. Embed. Syst., 2006
Automated derivation of NoC Communication Specifications from Application Constraints.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Secure Architecture in Embedded Systems: an Overview.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
RTOS extensions for dynamic hardware / software monitoring and configuration management.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
2005
J. VLSI Signal Process., 2005
Design-Trotter: System-level dynamic estimation task a first step towards platform architecture selection.
J. Embed. Comput., 2005
Adv. Eng. Softw., 2005
Feedback control modelling for learning reconfigurable embedded systems.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
2004
Comput. Stand. Interfaces, 2004
2003
Estimation du parallélisme au niveau système pour l'exploration de l'espace de conception de systèmes enfouis.
Tech. Sci. Informatiques, 2003
Proceedings of the 2003 Design, 2003
2002
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
Proceedings of the IEEE 5th Workshop on Multimedia Signal Processing, 2002
2001
Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 2001
2000
J. VLSI Signal Process., 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1998
Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1996
Proceedings of the 8th European Signal Processing Conference, 1996