Jean Oudinot

According to our database, Jean Oudinot authored at least 9 papers between 2002 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Application of Bottom-Up Methodology to RTW VCO.

Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2006

Top Verification of Low Power System with "Checkerboard" Approach.

Jean Oudinot

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Hierarchical Modeling of a Fractional Phase Locked Loop.

Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Scalable Model for Multi-Standard Phase Locked Loop.

Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004

SoC modelling for virtual prototyping with VHDL-AMS.

Patricia Desgreys, Yannick Hervé, Jean Oudinot, S. Snaidero, Mohamed Karray

Proceedings of the Forum on specification and Design Languages, 2004

VHDL-AMS Library Development for Pacemaker Applications.

B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot

Proceedings of the 2004 Design, 2004

2003

The Most Complete Mixed-Signal Simulation Solution with ADVance MS.

Jean Oudinot

Proceedings of the Integrated Circuit and System Design, 2003

Micromotor Simulation with VHDL-AMS.

Jean Oudinot, G. Overton, Aitor Endemaño Isasi, Marc P. Y. Desmulliez, Jean-Yves Fourniols, Sylvaine Muratet

Proceedings of the Forum on specification and Design Languages, 2003

2002

Full Transceiver Circuit Simulation using VHDL-AMS.

Jean Oudinot, Serge Scotti, Jean Ravatin, Audrey Le-clercq, Jacky Lebrun

Proceedings of the 16^th European Simulation Multiconference: Modelling and Simulation 2002, 2002