Jean-Olivier Plouchart

IEEE J. Solid State Circuits, September, 2024

2023

Cryogenic CMOS: design considerations for future quantum computing systems.

[BibT_eX]

[DOI]

Rajiv V. Joshi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

2018

Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.

[BibT_eX]

[DOI]

Wooram Lee

IEEE J. Solid State Circuits, 2018

Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions.

[BibT_eX]

[DOI]

Xiaoxiong Gu

Mark Yeck

Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017

An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI.

[BibT_eX]

[DOI]

Jen-Chieh Hsueh

Vanessa H.-C. Chen

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015

Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information.

[BibT_eX]

[DOI]

Fa Wang

Manzil Zaheer

Xin Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.

[BibT_eX]

[DOI]

Benjamin D. Parker

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.

[BibT_eX]

[DOI]

Fa Wang

Xin Li

Benjamin D. Parker

Andreea Balteanu

IEEE Des. Test, 2014

2013

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.

[BibT_eX]

[DOI]

Benjamin D. Parker

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs.

[BibT_eX]

[DOI]

Gokce Keskin

Jonathan E. Proesel

Lawrence T. Pileggi

IEEE J. Solid State Circuits, 2011

A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI.

[BibT_eX]

[DOI]

Scott K. Reynolds

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection.

[BibT_eX]

[DOI]

Jonathan E. Proesel

Gokce Keskin

Lawrence T. Pileggi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.

[BibT_eX]

[DOI]

John F. Bulzacchelli

Zeynep Toprak Deniz

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS.

[BibT_eX]

[DOI]

Mahender Kumar

Woo-Hyeong Lee

Ken Rim

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.

[BibT_eX]

[DOI]

Didem Zeliha Turker

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Wideband mmWave CML static divider in 65nm SOI CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS.

[BibT_eX]

[DOI]

Daihyun Lim

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.

[BibT_eX]

[DOI]

Daihyun Lim

Sangyeun Cho

Robert Trzcinski

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Statistical Framework for Technology-Model-Product Co-Design and Convergence.

[BibT_eX]

[DOI]

Robert Trzcinski

Proceedings of the 44th Design Automation Conference, 2007

2006

Performance Variations of a 66GHz Static CML Divider in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement.

[BibT_eX]

[DOI]

Robert Trzcinski

David Ahlgren

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004

A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology.

[BibT_eX]

[DOI]

Neric H. W. Fong

IEEE J. Solid State Circuits, 2004

Design and manufacturability aspect of SOI CMOS RFICs.

[BibT_eX]

[DOI]

Noah Zamdmer

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Design of wide-band CMOS VCO for multiband wireless LAN applications.

[BibT_eX]

[DOI]

Neric H. W. Fong

IEEE J. Solid State Circuits, 2003

Frequency-independent equivalent-circuit model for on-chip spiral inductors.

[BibT_eX]

[DOI]

Richard A. Wachnik

Tsu-Jae King

Chenming Hu

IEEE J. Solid State Circuits, 2003

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2003

A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS.

[BibT_eX]

[DOI]

Neric H. W. Fong

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits.

[BibT_eX]

[DOI]

Mehmet Soyuer

Mounir Meghelli

Proc. IEEE, 2000

1999

A 5.2 GHz 3.3 V I/Q SiGe RF transceiver.

[BibT_eX]

[DOI]