Jean-Michel Portal

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Memristor-Based Bayesian Machine.

[BibT_eX]

[DOI]

CoRR, 2021

Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.

[BibT_eX]

[DOI]

CoRR, 2021

A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

A Self-referenced and regulated sensing solution for PCM with OTS selector.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2021

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

[BibT_eX]

[DOI]

César Fuguet Tortolero

Eric Guthmuller

Mathieu Moreau

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.

[BibT_eX]

[DOI]

CoRR, 2020

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.

[BibT_eX]

[DOI]

IEEE Access, 2020

Embracing the Unreliability of Memory Devices for Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.

[BibT_eX]

[DOI]

Axel Laborieux

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.

[BibT_eX]

[DOI]

CoRR, 2019

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2019

Stochastic Computing for Hardware Implementation of Binarized Neural Networks.

[BibT_eX]

[DOI]

Damien Querlioz

IEEE Access, 2019

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.

[BibT_eX]

[DOI]

Mounia Kharbouche-Harrari

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis.

[BibT_eX]

[DOI]

Mounia Kharbouche-Harrari

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM.

[BibT_eX]

[DOI]

Romain Wacquez

Gregory di Pendina

Jean-Max Dutertre

Driss Aboulkassimi

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Memory-Centric Neuromorphic Computing With Nanodevices.

[BibT_eX]

[DOI]

Damien Querlioz

Julie Grollier

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.

[BibT_eX]

[DOI]

Mounia Kharbouche-Harrari

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018

An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Reliable ReRAM-based Logic Operations for Computing in Memory.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Resistive and Spintronic RAMs: Device, Simulation, and Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.

[BibT_eX]

[DOI]

Pascal Andreas Meinerzhagen

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps.

[BibT_eX]

[DOI]

J. Low Power Electron., 2017

High voltage recycling scheme to improve power consumption of regulated charge pumps.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Architecture, design and technology guidelines for crosspoint memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

High density emerging resistive memories: What are the limits?

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Thermal laser attack and high temperature heating on HfO2-based OxRAM cells.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

Resistive RAM variability monitoring using a ring oscillator based test chip.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Optimization of a Particles Detection Chain Based on a VCO Structure.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Multilevel operation in oxide based resistive RAM with SET voltage modulation.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015

Improvement of MOSFET matching characterization with calibrated multiplexed test structure.

[BibT_eX]

[DOI]

Loic Welter

J. L. Scotto di Quaquero

Microelectron. Reliab., 2015

Dynamic current reduction of CMOS digital circuits through design and process optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.

[BibT_eX]

[DOI]

Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Layout optimizations to decrease internal power and area in digital CMOS standard cells.

[BibT_eX]

[DOI]

Proceedings of the 38th International Convention on Information and Communication Technology, 2015

Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

2014

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

RRAM-based FPGA for "Normally Off, Instantly On" applications.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2014

OxRAM-based non volatile flip-flop in 28nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Improvement of a VCO concept for low energy particule detection and recognition.

[BibT_eX]

[DOI]

Proceedings of the 15th Latin American Test Workshop, 2014

An innovative standard cells remapping method for in-circuit critical parameters monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Printed complementary organic thin film transistors based decoder for ferroelectric memory.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2014, 2014

Accurate multiplexed test structure for threshold voltage matching evaluation.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Resistive memories: Which applications?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A novel test structure for OxRRAM process variability evaluation.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2013

On the investigation of built-in tuning of RF receivers using on-chip polyphase filters.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Synchronous full-adder based on complementary resistive switching memory cells.

[BibT_eX]

[DOI]

Yue Zhang

Erya Deng

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

DCG-FGT transistor: Retention study of Floating Gate charge.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

SPICE level analysis of Single Event Effects in an OxRRAM cell.

[BibT_eX]

[DOI]

Christophe Muller

Proceedings of the 14th Latin American Test Workshop, 2013

A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Embedded high-precision frequency-based capacitor measurement system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Single-ended sense amplifier robustness evaluation for OxRRAM technology.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Low-cost auto-calibration of passive polyphase filter in image reject receiver.

[BibT_eX]

[DOI]

Jamel Nebhen

Hervé Barthélemy

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.

[BibT_eX]

[DOI]

Pascal Masson

J. Low Power Electron., 2012

Optimization of SEU Simulations for SRAM Cells Reliability under Radiation.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.

[BibT_eX]

[DOI]

Weisheng Zhao

Yue Zhang

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT).

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

SITARe: A simulation tool for analysis and diagnosis of radiation effects.

[BibT_eX]

[DOI]

Proceedings of the 13th Latin American Test Workshop, 2012

Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring.

[BibT_eX]

[DOI]

Proceedings of the 13th Latin American Test Workshop, 2012

Investigation of a CMOS oscillator concept for particle detection and diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 13th Latin American Test Workshop, 2012

PSP based DCG-FGT transistor Model: Full characterization procedure.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

Back-end soft and hard defect monitoring using a single test chip.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.

[BibT_eX]

[DOI]

Santhosh Onkaraiah

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Impact of SEU configurations on a SRAM cell response at circuit level.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Analysis of SEU parameters for the study of SRAM cells reliability under radiation.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Bipolar OxRRAM memory array reliability evaluation based on fault injection.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

PSP based DCG-FGT transistor model including characterization procedure.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design challenges for prototypical and emerging memory concepts relying on resistance switching.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009

Definition of an innovative filling structure for digital blocks : the DFM filler cell.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections.

[BibT_eX]

[DOI]

Olivier Ginez

Christophe Muller

Proceedings of the 14th IEEE European Test Symposium, 2009

An on-line testing scheme for repairing purposes in Flash memories.

[BibT_eX]

[DOI]

Olivier Ginez

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A Novel Low Power Oriented Design Methodology for Analog Blocks.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Metal filling impact on standard cells: definition of the metal fill corner concept.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories.

[BibT_eX]

[DOI]

Olivier Ginez

Proceedings of the 2008 IEEE International Test Conference, 2008

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2006

MM11 based flash memory cell model including characterization procedure.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.

[BibT_eX]

[DOI]

B. Saillet

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A New Embedded Measurement Structure for eDRAM Capacitor.

[BibT_eX]

[DOI]

Laurent Lopez

Proceedings of the 2005 Design, 2005

2004

Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture.

[BibT_eX]

Anna Labbé

Annie Pérez

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology.

[BibT_eX]

[DOI]

Sandrine Bernardini

Pascal Masson

Proceedings of the 2004 Design, 2004

2003

EEPROM Memory: Threshold Voltage Built In Self Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Infrastructure IP for Back-End Yield Improvement.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

An Automated Design Methodology for EEPROM Cell (ADE).

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Floating-gate EEPROM cell model based on MOS model 9.

[BibT_eX]

[DOI]

L. Forli

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Floating-gate EEPROM cell: threshold voltage sensibility to geometry.

[BibT_eX]

[DOI]

L. Forli

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Analyzing bridging faults impact on EEPROM cell array.

[BibT_eX]

[DOI]