Jean-Marc Philippe
Orcid: 0000-0002-6062-8145
According to our database1,
Jean-Marc Philippe
authored at least 27 papers
between 2005 and 2023.
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Bibliography
2023
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration.
IEEE J. Solid State Circuits, 2023
A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
J. Signal Process. Syst., 2022
2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Analysis of on-chip communication properties in accelerator architectures for deep neural networks.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
2020
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
2018
Task management on fully heterogeneous micro-server system: Modeling and resolution strategies.
Concurr. Comput. Pract. Exp., 2018
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Microprocess. Microsystems, 2017
Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
2013
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture.
Proceedings of the Design, Automation and Test in Europe, 2013
2010
Microelectron. J., 2010
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010
2008
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
2007
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
Proceedings of the FPL 2007, 2007
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A low-power and high-speed quaternary interconnection link using efficient converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005