Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies.

[BibT_eX]

[DOI]

Amit Karel

Florence Azaïs

Mariane Comte

Jean-Marc Gallière

Michel Renovell

J. Electron. Test., 2019

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

2018

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection.

[BibT_eX]

[DOI]

Maxime Cozzi

Jean-Marc Gallière

Philippe Maurine

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Thermal Scans for Detecting Hardware Trojans.

[BibT_eX]

[DOI]

Maxime Cozzi

Jean-Marc Gallière

Philippe Maurine

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018

2017

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies.

[BibT_eX]

[DOI]

J. Electron. Test., 2017

Analysis of short defects in FinFET based logic cells.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2014

Testing for gate oxide short defects using the detectability interval paradigm.

[BibT_eX]

[DOI]

it Inf. Technol., 2014

2013

A toolkit to demystify CMOS Active Pixel Sensors.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Jerome Boch

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2011

Versatile march test generator for hands-on memory testing laboratory.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Luigi Dilillo

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

2010

A roaming memory test bench for detecting particle induced SEUs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

A mixed TCAD/Electrical simulation laboratory to open up the microelectronics teaching.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Jerome Boch

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2008

A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Philippe Papet

Laurent Latorre

Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2007

Stream Manager, Easy CAD Tools Switching in Academic Context.

[BibT_eX]

[DOI]

Jean-Marc Gallière

Guy Cathébras

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2005

Delay Testing Viability of Gate Oxide Short Defects.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2003

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Delay Testing of MOS Transistor with Gate Oxide Short.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Modeling gate oxide short defects in CMOS minimum transistors.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

2001

Electrical Analysis of Gate Oxide Short in MOS Technologies.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

Boolean and current detection of MOS transistor with gate oxide short.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Jean-Marc Gallière

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...