Jean-Luc Danger
Orcid: 0000-0001-5063-7964Affiliations:
- Télécom Paris, France
According to our database1,
Jean-Luc Danger
authored at least 236 papers
between 1999 and 2024.
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Bibliography
2024
IEEE Trans. Computers, October, 2024
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024
2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023
Proceedings of the Advances in Information and Computer Security, 2023
Proceedings of the Fourteenth International Conference on Ubiquitous and Future Networks, 2023
Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks.
Proceedings of the International Conference on IC Design and Technology, 2023
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Information Leakage in Code-Based Masking: A Systematic Evaluation by Higher-Order Attacks.
IEEE Trans. Inf. Forensics Secur., 2022
Interleaved Challenge Loop PUF: A Highly Side-Channel Protected Oscillator-Based PUF.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
J. Electron. Test., 2022
AVTPnet: Convolutional Autoencoder for AVTP anomaly detection in Automotive Ethernet Networks.
CoRR, 2022
On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis.
Proceedings of the 19th International Conference on Security and Cryptography, 2022
Unsupervised Network Intrusion Detection System for AVTP in Automotive Ethernet Networks.
Proceedings of the 2022 IEEE Intelligent Vehicles Symposium, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
CAN-BERT do it? Controller Area Network Intrusion Detection System based on BERT Language Model.
Proceedings of the 19th IEEE/ACS International Conference on Computer Systems and Applications, 2022
2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021
IEEE Trans. Inf. Forensics Secur., 2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
J. Electron. Test., 2021
SOME/IP Intrusion Detection using Deep Learning-based Sequential Models in Automotive Ethernet Networks.
CoRR, 2021
Cryptogr. Commun., 2021
CAAI Trans. Intell. Technol., 2021
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021
Water- PUF: An Insider Threat Resistant PUF Enrollment Protocol Based on Machine Learning Watermarking.
Proceedings of the 20th IEEE International Symposium on Network Computing and Applications, 2021
Laser Fault Injection in a 32-bit Microcontroller: from the Flash Interface to the Execution Pipeline.
Proceedings of the 18th Workshop on Fault Detection and Tolerance in Cryptography, 2021
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Enhancing the Resiliency of Multi-bit Parallel Arbiter-PUF and Its Derivatives Against Power Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021
Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks.
Proceedings of the Applied Cryptography and Network Security, 2021
2020
IEEE Trans. Computers, 2020
IACR Cryptol. ePrint Arch., 2020
Challenge codes for physically unclonable functions with Gaussian delays: A maximum entropy problem.
Adv. Math. Commun., 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the IEEE International Test Conference, 2020
On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 17th Workshop on Fault Detection and Tolerance in Cryptography, 2020
Proceedings of the IEEE European Test Symposium, 2020
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
IACR Cryptol. ePrint Arch., 2019
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
IEEE Trans. Inf. Forensics Secur., 2018
J. Hardw. Syst. Secur., 2018
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller.
IACR Cryptol. ePrint Arch., 2018
On the Performance and Security of Multiplication in <i>GF</i>(2<sup><i>N</i></sup>).
Cryptogr., 2018
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers.
Proceedings of the Information Security Theory and Practice, 2018
Prediction-Based Intrusion Detection System for In-Vehicle Networks Using Supervised Learning and Outlier-Detection.
Proceedings of the Information Security Theory and Practice, 2018
Development of the Unified Security Requirements of PUFs During the Standardization Process.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Cyber-Physical Systems Security., 2018
Proceedings of the Cyber-Physical Systems Security., 2018
Proceedings of the Cyber-Physical Systems Security., 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis.
J. Cryptogr. Eng., 2016
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
IACR Cryptol. ePrint Arch., 2016
Correlated Extra-Reductions Defeat Blinded Regular Exponentiation - Extended Version.
IACR Cryptol. ePrint Arch., 2016
Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016
Proceedings of the IEEE International Symposium on Information Theory, 2016
Proceedings of the IEEE International Symposium on Information Theory, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2016
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016
Proceedings of the New Codebreakers, 2016
2015
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Reconfigurable Technol. Syst., 2015
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Multiply Constant-Weight Codes and the Reliability of Loop Physically Unclonable Functions.
IEEE Trans. Inf. Theory, 2014
J. Math. Cryptol., 2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014
J. Cryptogr. Eng., 2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the Information Security Theory and Practice. Securing the Internet of Things, 2014
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014
Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding.
Proceedings of the 3rd ACM SIGPLAN Program Protection and Reverse Engineering Workshop 2014, 2014
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.
Proceedings of the HASP 2014, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the First Workshop on Cryptography and Security in Computing Systems, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014
Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
Proceedings of the 4th Program Protection and Reverse Engineering Workshop, 2014
2013
J. Cryptogr. Eng., 2013
J. Cryptogr. Eng., 2013
From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications.
J. Cryptogr. Eng., 2013
IACR Cryptol. ePrint Arch., 2013
IACR Cryptol. ePrint Arch., 2013
Proceedings of the Trust and Trustworthy Computing - 6th International Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013
Proceedings of the HASP 2013, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2013
A low-entropy first-degree secure provable masking scheme for resource-constrained devices.
Proceedings of the Workshop on Embedded Systems Security, 2013
2012
Proceedings of the Fault Analysis in Cryptography, 2012
Int. J. Reconfigurable Comput., 2012
IACR Cryptol. ePrint Arch., 2012
Proceedings of the Information Security Theory and Practice. Security, Privacy and Trust in Computing Systems and Ambient Intelligent Ecosystems, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the Information Systems, Technology and Management, 2012
Proceedings of the Information and Communications Security - 14th International Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
Proceedings of the Smart Card Research and Advanced Applications, 2012
2011
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks.
IET Inf. Secur., 2011
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2011
Classification of High-Order Boolean Masking Schemes and Improvements of their Efficiency.
IACR Cryptol. ePrint Arch., 2011
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
CoRR, 2011
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011
Proceedings of the 2011 IEEE International Workshop on Information Forensics and Security, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Security Aspects in Information Technology, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Int. J. Reconfigurable Comput., 2010
Proceedings of the Information Security Applications - 11th International Workshop, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Information Security and Cryptology - ICISC 2010, 2010
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.
Proceedings of the Topics in Cryptology, 2010
Proceedings of the Information Security and Cryptology - 6th International Conference, 2010
Proceedings of the 5th Workshop on Embedded Systems Security, 2010
2009
On the Implementation of a Probabilistic Equalizer for Low-Cost Impulse Radio UWB in High Data Rate.
Wirel. Sens. Netw., 2009
Microelectron. J., 2009
Protecting the NOEKEON Cipher Against SCARE Attacks in FPGAs by using Dynamic Implementations.
IACR Cryptol. ePrint Arch., 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
CoRR, 2008
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008
Proceedings of the NTMS 2008, 2008
Proceedings of the 2008 5th International Symposium on Wireless Communication Systems, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.
Proceedings of the FPL 2008, 2008
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008
Proceedings of the Seventh European Dependable Computing Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference.
Proceedings of the 2007 IEEE International Conference on Research, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the FPL 2007, 2007
2006
IEEE Wirel. Commun., 2006
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
2005
Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections.
Proceedings of the IEEE 16th International Symposium on Personal, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004
2002
Proceedings of the IEEE International Conference on Communications, 2002
2000
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Efficient FPGA implementation of Gaussian noise generator for communication channel emulation.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
1999
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999