Jean-François Nodin

According to our database1, Jean-François Nodin authored at least 13 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
Investigation of resistance fluctuations in ReRAM: physical origin, temporal dependence and impact on memory reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device array.
Proceedings of the IEEE International Memory Workshop, 2023

2022
A High Throughput Generative Vector Autoregression Model for Stochastic Synapses.
CoRR, 2022

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022


2021
A Comprehensive Oxide-Based ReRAM TCAD Model with Experimental Verification.
Proceedings of the IEEE International Memory Workshop, 2021

2020
Fully-Integrated Spiking Neural Network Using SiOx-Based RRAM as Synaptic Device.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2018
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2013
Back-end 3D integration of HfO2-based RRAMs for low-voltage advanced IC digital design.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

On the forming-free operation of HfOx based RRAM devices: Experiments and ab initio calculations.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
High temperature reliability of μtrench Phase-Change Memory devices.
Microelectron. Reliab., 2012

Carbon-doped Ge2Sb2Te5 phase-change memory devices featuring reduced RESET current and power consumption.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


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