Jean-Didier Legat
Orcid: 0000-0001-7147-5124
According to our database1,
Jean-Didier Legat
authored at least 94 papers
between 1992 and 2020.
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Bibliography
2020
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 0.086-mm<sup>2</sup> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2019
MorphIC: A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning.
IEEE Trans. Biomed. Circuits Syst., 2019
A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 0.086-mm<sup>2</sup> 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS.
CoRR, 2018
2017
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectron. J., 2016
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
2015
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
2014
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electron., 2014
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
SleepWalker: A 25-MHz 0.4-V Sub-mm<sup>2</sup> 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.
IEEE J. Solid State Circuits, 2013
An efficient metric of setup time for pulsed flip-flops based on output transition time.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks.
Int. J. Reconfigurable Comput., 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptogr. Eng., 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Combining sdm-based circuit switching with packet switching in a NoC for real-time applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels.
ACM Trans. Design Autom. Electr. Syst., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Combining circuit and packet switching with bus architecture in a NoC for real-time applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Flexible embedded system for sensor integration and custom data processing in an automotive application.
Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications.
EURASIP J. Embed. Syst., 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
J. Multiple Valued Log. Soft Comput., 2007
Dynamic differential self-timed logic families for robust and low-power security ICs.
Integr., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
IEEE Trans. Circuits Syst. Video Technol., 2006
Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks.
Microelectron. J., 2006
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
J. Low Power Electron., 2006
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
2004
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.
Proceedings of the Integrated Circuit and System Design, 2004
Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004
ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware.
Proceedings of the Fast Software Encryption, 11th International Workshop, 2004
Proceedings of the 2004 12th European Signal Processing Conference, 2004
Proceedings of the 2004 12th European Signal Processing Conference, 2004
Reconfigurable hardware solutions for the digital rights management of digital cinema.
Proceedings of the 2004 ACM Workshop on Digital Rights Management 2004, Washington, 2004
2003
IEEE Trans. Circuits Syst. Video Technol., 2003
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis.
IEEE Trans. Computers, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the 11th European Signal Processing Conference, 2002
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002
2001
Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
2000
Integr. Comput. Aided Eng., 2000
1999
Proceedings of the Security and Watermarking of Multimedia Contents, 1999
Fine grain parallelization of multibody system equations of motion.
Proceedings of the Parallel Computing: Fundamentals & Applications, 1999
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Proceedings of the Parallel Computation, 1999
1998
J. VLSI Signal Process., 1998
Signal Process. Image Commun., 1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Efficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998
1996
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996
1995
Proceedings of the From Natural to Artificial Neural Computation, 1995
Proceedings of the From Natural to Artificial Neural Computation, 1995
Proceedings of the From Natural to Artificial Neural Computation, 1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
Proceedings of the 3rd European Symposium on Artificial Neural Networks, 1995
1993
IEEE Trans. Neural Networks, 1993
Systolic implementation of a bidimensional lattice filter bank for multiresolution image coding.
Proceedings of the Visual Communications and Image Processing '93, 1993
Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns.
Proceedings of the New Trends in Neural Computation, 1993
Proceedings of the 1st European Symposium on Artificial Neural Networks, 1993
1992
Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992