Jean-Claude Bajard
Orcid: 0000-0002-6301-4464
According to our database1,
Jean-Claude Bajard
authored at least 54 papers
between 1993 and 2024.
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Bibliography
2024
Adv. Math. Commun., 2024
2023
Fast verification and public key storage optimization for unstructured lattice-based signatures.
J. Cryptogr. Eng., September, 2023
2022
2021
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021
2020
IEEE Trans. Inf. Forensics Secur., 2020
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020
2019
Resilience of Randomized RNS Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation.
IEEE Trans. Computers, 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
J. Cryptogr. Eng., 2018
IACR Cryptol. ePrint Arch., 2018
2017
Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices.
IEEE Trans. Computers, 2017
IACR Cryptol. ePrint Arch., 2017
Efficient Reductions in Cyclotomic Rings - Application to Ring-LWE Based FHE Schemes.
Proceedings of the Selected Areas in Cryptography - SAC 2017, 2017
2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
RNS Arithmetic Approach in Lattice-Based Cryptography: Accelerating the "Rounding-off" Core Procedure.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015
2014
IACR Cryptol. ePrint Arch., 2014
Babaï round-off CVP method in RNS: Application to lattice based cryptographic protocols.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013
2012
IEEE Trans. Computers, 2012
Comput. J., 2012
2011
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
2010
Subquadratic Space Complexity Binary Field Multiplier Using Double Polynomial Representation.
IEEE Trans. Computers, 2010
IACR Cryptol. ePrint Arch., 2010
Combining leak-resistant arithmetic for elliptic curves defined over F<sub>p</sub> and RNS representation.
IACR Cryptol. ePrint Arch., 2010
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
IACR Cryptol. ePrint Arch., 2009
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
2006
Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the Lagrange Representation.
IEEE Trans. Computers, 2006
A Parallel and Secure Architecture for Asymmetric Cryptography.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2005
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
Parallel Montgomery Multiplication in GF(2<sup>k</sup>) using Trinomial Residue Arithmetic.
IACR Cryptol. ePrint Arch., 2004
Proceedings of the Selected Areas in Cryptography, 11th International Workshop, 2004
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004
2003
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
2002
Proceedings of the Progress in Cryptology, 2002
2001
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001
1999
1998
J. VLSI Signal Process., 1998
1997
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997
1996
Forword to the Special Issue on Real Numbers and Computers.
Theor. Comput. Sci., 1996
1995
J. Univers. Comput. Sci., 1995
1994
IEEE Trans. Computers, 1994
J. Parallel Distributed Comput., 1994
1993
A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functions.
Proceedings of the VLSI 93, 1993
Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions.
Proceedings of the International Conference on Application-Specific Array Processors, 1993