Jean-Baptiste Rigaud

Orcid: 0000-0001-7394-5345

According to our database¹, Jean-Baptiste Rigaud authored at least 55 papers between 2001 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Other

Bibliography

2024

EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Using a Performance Model to Implement a Superscalar CVA6.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

Experimental EMFI detection on a RISC-V core using the Trace Verifier solution.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2023

CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023

Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A CCFI Verification Scheme Based on the RISC-V Trace Encoder.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023

Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2023

2022

An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation.

[BibT_eX]

[DOI]

William Souza da Cruz

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

A CFI Verification System based on the RISC-V Instruction Trace Encoder.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2022

2021

A Review of Confidentiality Threats Against Embedded Neural Network Models.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Hardware Implementation of Multiplication over Quartic Extension Fields.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Mathematics and Computing, 2021

Hardware Implementations of Pairings at Updated Security Levels.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2021

Further Analysis of Laser-induced IR-drop.

[BibT_eX]

[DOI]

William Souza da Cruz

Raphael Andreoni Camponogara Viera

Jean-Max Dutertre

Jean-Baptiste Rigaud

Guillaume Hubert

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Evidence of a Dynamic Fault Model in the DICE Radiation-Hardened Cell.

[BibT_eX]

[DOI]

William Souza da Cruz

Jean-Max Dutertre

Jean-Baptiste Rigaud

Guillaume Hubert

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Single-bit Laser Fault Model in NOR Flash Memories: Analysis and Exploitation.

[BibT_eX]

[DOI]

Proceedings of the 17th Workshop on Fault Detection and Tolerance in Cryptography, 2020

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model.

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019

Experimental Analysis of the Laser-Induced Instruction Skip Fault Model.

[BibT_eX]

[DOI]

Proceedings of the Secure IT Systems, 2019

Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers.

[BibT_eX]

[DOI]

Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

2018

Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

2017

A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

2016

A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Body Biasing Injection Attacks in Practice.

[BibT_eX]

[DOI]

Noemie Beringuier-Boher

Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016

An Embedded Digital Sensor against EM and BB Fault Injection.

[BibT_eX]

[DOI]

David El-Baze

Jean-Baptiste Rigaud

Philippe Maurine

Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults.

[BibT_eX]

[DOI]

Marc Lacruche

Noemie Beringuier-Boher

Jean-Max Dutertre

Jean-Baptiste Rigaud

Edith Kussener

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fully-digital EM pulse detector.

[BibT_eX]

[DOI]

David El-Baze

Jean-Baptiste Rigaud

Philippe Maurine

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication.

[BibT_eX]

[DOI]

Proceedings of the Risks and Security of Internet and Systems, 2016

2015

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Resilient hardware Trojans detection based on path delay measurements.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Evidence of an information leakage between logically independent blocks.

[BibT_eX]

[DOI]

Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015

Hardware trojan detection by delay and electromagnetic measurements.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Analysis Of Variance and CPA in SCA.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Power supply glitch attacks: Design and evaluation of detection circuits.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Detecting positive voltage attacks on CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Cryptography and Security in Computing Systems, 2014

Voltage Glitch Attacks on Mixed-Signal Systems.

[BibT_eX]

[DOI]

Noemie Beringuier-Boher

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Power analysis methodology for secure circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2011

Design and characterisation of an AES chip embedding countermeasures.

[BibT_eX]

[DOI]

Jacques J. A. Fournier

Int. J. Intell. Eng. Informatics, 2011

A side-channel and fault-attack resistant AES circuit working on duplicated complemented values.

[BibT_eX]

[DOI]

Marion Doulcier-Verdier

Jean-Max Dutertre

Jacques J. A. Fournier

Jean-Baptiste Rigaud

Bruno Robisson

Assia Tria

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Experimental Fault Injection based on the Prototyping of an AES Cryptosystem.

[BibT_eX]

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

2008

Error Detection for Borrow-Save Adders Dedicated to ECC Unit.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

2007

Strengthening hardware AES implementations against fault attacks.

[BibT_eX]

[DOI]

Marc Joye

Pascal Manet

Jean-Baptiste Rigaud

IET Inf. Secur., 2007

Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Integrated Evaluation Platform for Secured Devices.

[BibT_eX]

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2005

Hardware Engines for Bus Encryption: A Survey of Existing Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2003

Statistic Implementation of QDI Asynchronous Primitives.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

2002

Spécification de bibliothèques pour la synthèse de circuits asynchrones. (Libraries specification for the synthesis of asynchronous circuits).

[BibT_eX]

[DOI]

Jean-Baptiste Rigaud

PhD thesis, 2002

Implementing Asynchronous Circuits on LUT Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

Jean-Baptiste Rigaud

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