Je-Joong Woo

According to our database, Je-Joong Woo authored at least 4 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device.

Jong-Moon Choi, Do-Wan Kwon, Je-Joong Woo, Eun-Je Park, Kee-Won Kwon

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition.

Eun-Je Park, Jong-Moon Choi, Do-Wan Kwon, Je-Joong Woo, Kee-Won Kwon

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections.

Je-Joong Woo, Jong-Moon Choi, Kee-Won Kwon

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.

Yong-Hyun Kim, Jong-Moon Choi, Je-Joong Woo, Eun-Je Park, Sang-Won Kim, Kee-Won Kwon

Proceedings of the International Conference on Electronics, Information, and Communication, 2019