Je-Ching Liu

According to our database, Je-Ching Liu authored at least 2 papers in 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.

Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang

IEEE J. Solid State Circuits, 2010

A 55nm 1GHz one-cycle-locking de-skewing circuit.

Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010