Jaynarayan T. Tudu

Lakshmi Bhanuprakash Reddy Konduru

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2022

Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption.

[BibT_eX]

[DOI]

Vijaya Lakshmi

CoRR, 2022

On Protecting IJTAG from Data Sniffing and Alteration Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

A Framework for Configurable Joint-Scan Design-for-Test Architecture.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

2020

LUT-based Circuit Approximation with Targeted Error Guarantees.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Securing Scan through Plain-text Restriction.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Preventing Scan Attack through Test Response Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

On Securing Scan Design Through Test Vector Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A Cost Effective Technique for Diagnosis of Scan Chain Faults.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Revisiting random access scan for effective enhancement of post-silicon observability.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

On Securing Scan Design from Scan-Based Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Guided shifting of test pattern to minimize test time in serial scan.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

On determination of instantaneous peak and cycle peak switching using ILP.

[BibT_eX]

[DOI]

Rohini Gulve

Nihar Hage

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

On minimization of test power through modified scan flip-flop.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Skip-scan: A methodology for test time reduction.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A high performance scan flip-flop design for serial and mixed mode scan test.

[BibT_eX]

[DOI]

Anzhela Yu. Matrosova

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan.

[BibT_eX]

[DOI]

Anzhela Yu. Matrosova

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2013

Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP.

[BibT_eX]

[DOI]

Deepak Malani

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012

ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits.

[BibT_eX]

[DOI]

Deepak Malani