Jayesh Wadekar
According to our database1,
Jayesh Wadekar
authored at least 2 papers
between 2012 and 2016.
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Bibliography
2016
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2012
A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching.
Proceedings of the 38th European Solid-State Circuit conference, 2012