Jayesh Gaur

According to our database, Jayesh Gaur authored at least 19 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution.

Rahul Bera, Adithya Ranganathan, Joydeep Rakshit, Sujit Mahto, Anant V. Nori, Jayesh Gaur, Ataberk Olgun, Konstantinos Kanellopoulos, Mohammad Sadrosadati, Sreenivas Subramoney, Onur Mutlu

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2022

Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations.

Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Register file prefetching.

Sudhanshu Shukla, Sumeet Bandishte, Jayesh Gaur, Sreenivas Subramoney

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

Cryptographic Capability Computing.

Michael LeMay, Joydeep Rakshit, Sergej Deutsch, David M. Durham, Santosh Ghosh, Anant Nori, Jayesh Gaur, Andrew Weiler, Salmin Sultana, Karanvir Grewal, Sreenivas Subramoney

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Stream Floating: Enabling Proactive and Decentralized Cache Optimizations.

Zhengrong Wang, Jian Weng, Jason Lowe-Power, Jayesh Gaur, Tony Nowatzki

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

Auto-Predication of Critical Branches.

Adarsh Chauhan, Jayesh Gaur, Zeev Sperber, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Focused Value Prediction.

Sumeet Bandishte, Jayesh Gaur, Zeev Sperber, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019

Post-silicon CPU adaptation made practical using machine learning.

Stephen J. Tarsa, Rangeen Basu Roy Chowdhury, Julien Sebot, Gautham N. Chinya, Jayesh Gaur, Karthik Sankaranarayanan, Chit-Kwan Lin, Robert Chappell, Ronak Singhal, Hong Wang

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth.

Mainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

MARS: Memory Aware Reordered Source.

Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang

CoRR, 2018

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies.

Anant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.

Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches.

Mainak Chaudhuri, Mukesh Agrawal, Jayesh Gaur, Sreenivas Subramoney

ACM Trans. Archit. Code Optim., 2017

Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources.

Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016

Base-Victim Compression: An Opportunistic Cache Compression Architecture.

Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2013

Efficient management of last-level caches in graphics processors for 3D scene rendering workloads.

Jayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney, Mainak Chaudhuri

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches.

Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, Joseph Nuzman

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Bypass and insertion algorithms for exclusive last-level caches.

Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2007

Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation.

Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange

Proceedings of the 44th Design Automation Conference, 2007