Jaydeb Bhaumik

Orcid: 0000-0001-5382-9128

According to our database1, Jaydeb Bhaumik authored at least 34 papers between 2008 and 2024.

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Bibliography

2024
Performance Analysis of NR Polar Codes at Short Information Blocks for Control Channels.
Wirel. Pers. Commun., September, 2024

FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT.
J. Real Time Image Process., February, 2024

Improved DWT and IDWT architectures for image compression.
Microprocess. Microsystems, 2024

2023
An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads.
J. Signal Process. Syst., June, 2023

Construction Technique and Evaluation of High Performance t-bit Burst Error Correcting Codes for Protecting MCUs.
J. Circuits Syst. Comput., June, 2023

A new robust and fragile scheme based on chaotic maps and dwt for medical image security.
Multim. Tools Appl., March, 2023

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application.
Integr., March, 2023

Implementation of Fast and Power Efficient SEC-DAEC and SEC-DAEC-TAEC Codecs on FPGA.
CoRR, 2023

2022
A secure image encryption scheme based on three different chaotic maps.
Multim. Tools Appl., 2022

Joint video compression and encryption using parallel compressive sensing and improved chaotic maps.
Digit. Signal Process., 2022

A New Image Encryption Based on Two Chaotic Maps and Affine Transform.
Proceedings of the Computational Intelligence in Communications and Business Analytics, 2022

2021
An Image Authentication and Tampered Detection Scheme Exploiting Local Binary Pattern Along with Hamming Error Correcting Code.
Wirel. Pers. Commun., 2021

A secure reversible color image watermarking scheme based on LBP, lagrange interpolation polynomial and weighted matrix.
Multim. Tools Appl., 2021

A CAD approach for power supply noise aware floorplan in SoC.
Int. J. High Perform. Syst. Archit., 2021

Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip.
J. Electron. Test., 2021

Chaos-Based Uncompressed Frame Level Video Encryption.
Proceedings of the Seventh International Conference on Mathematics and Computing, 2021

Fast and Secure Video Encryption Using Divide-and-Conquer and Logistic Tent Infinite Collapse Chaotic Map.
Proceedings of the Computer Vision and Image Processing - 6th International Conference, 2021

2020
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs.
IET Comput. Digit. Tech., 2020

Design of SEC-DED and SEC-DED-DAEC Codes of different lengths.
CoRR, 2020

2019
Watermarking scheme using local binary pattern for image authentication and tamper detection through dual image.
Secur. Priv., 2019

Robust watermarking scheme for tamper detection and authentication exploiting CA.
IET Image Process., 2019

Fast and Power Efficient SEC-DED and SEC-DED-DAEC Codes in IoT based Wireless Sensor Networks.
Proceedings of the TENCON 2019, 2019

2018
Compact CA-Based Single Byte Error Correcting Codec.
IEEE Trans. Computers, 2018

A New SPN Type Architecture to Strengthen Block Cipher Against Fault Attack.
Int. J. Netw. Secur., 2018

2015
CA-Based Area Optimized Three Bytes Error Detecting Codes.
J. Cell. Autom., 2015

Synthesis of all Maximum Length Cellular Automata of Cell Size up to 12.
CoRR, 2015

2014
A Fault Based Attack on MDS-AES.
Int. J. Netw. Secur., 2014

2013
Rain: Reversible Addition with Increased Nonlinearity.
Int. J. Netw. Secur., 2013

2010
New Architectural Design of CA-Based Codec.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code.
Proceedings of the Cellular Automata, 2010

2009
An Integrated ECC-MAC Based on RS Code.
Trans. Comput. Sci., 2009

Nmix: An Ideal Candidate for Key Mixing.
Proceedings of the SECRYPT 2009, 2009

2008
Architectural Design of CA-Based Double Byte Error Correcting Codec.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

An Improved Double Byte Error Correcting Code Using Cellular Automata.
Proceedings of the Cellular Automata, 2008


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