Jayanand Asok Kumar
According to our database1,
Jayanand Asok Kumar
authored at least 12 papers
between 2010 and 2014.
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Bibliography
2014
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Scaling probabilistic timing verification of hardware using abstractions in design source code.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011
2010
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs.
Proceedings of the QEST 2010, 2010
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010