Jaya Dofe
Orcid: 0000-0003-1936-0455
According to our database1,
Jaya Dofe
authored at least 34 papers
between 2014 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
Protecting against modeling attacks: design and analysis of lightweight dynamic physical unclonable function.
Clust. Comput., February, 2025
2024
Natural Language Processing Meets Hardware Trojan Detection: Automating Security of FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024
2023
Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023
Counteracting Modeling Attacks Using Hardware-Based Dynamic Physical Unclonable Function.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023
2022
Thermal Side-channel Leakage Protection in Monolithic Three Dimensional Integrated Circuits.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 4th International Conference on Data Intelligence and Security, 2022
2021
Internet Things, 2021
LC-Physical Unclonable Function in Wireless 3D IC for Securing Internet of Things Devices.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2020
Comprehensive Analysis on Hardware Trojans in 3D ICs: Characterization and Experimental Impact Assessment.
SN Comput. Sci., 2020
Integr., 2020
2019
SRASA: a Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems.
J. Hardw. Syst. Secur., 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack.
J. Electron. Test., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Embed. Syst. Lett., 2015
Investigating power characteristics of memristor-based logic gates and their applications in a security primitive.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
VLSI Design, 2014