Jaya Deepthi Bandarupalli

According to our database, Jaya Deepthi Bandarupalli authored at least 3 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4MHz Reference and <30 ns Turn-On Time.

Jaya Deepthi Bandarupalli, Saurabh Saxena

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUI_rms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS.

Jaya Deepthi Bandarupalli, Saurabh Saxena

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2020

A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS.

R. Gautam, Jaya Deepthi Bandarupalli, Saurabh Saxena

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020