Jawar Singh

According to our database, Jawar Singh authored at least 46 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution.

Meena Panchore, Chithraja Rajan, Jawar Singh

J. Electron. Test., August, 2024

Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications.

V. Bharath Sreenivasulu, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh

IEEE Access, 2024

2023

An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications.

Abhash Kumar, Sai Manohar Beeraka, Jawar Singh, Bharat Gupta

Circuits Syst. Signal Process., May, 2023

Design and analysis of DDoS mitigating network architecture.

Swati, Sangita Roy, Jawar Singh, Jimson Mathew

Int. J. Inf. Sec., April, 2023

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison.

V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li

IEEE Access, 2023

A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact.

Ankit Sirohi, Jawar Singh

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

2022

A Framework for the Automation of Platform Validation for Use Cases of Wi-Fi.

Kota Nikhileswar, Sudhir Kumar, Jawar Singh, Dharmendra Muthuswamy

Proceedings of the IEEE International Conference on Industrial Technology, 2022

2020

In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications.

Abhash Kumar, Jawar Singh, Sai Manohar Beeraka, Bharat Gupta

CoRR, 2020

Blockchain-based Interoperable Healthcare using Zero-Knowledge Proofs and Proxy Re-Encryption.

Bhavye Sharma, Raju Halder, Jawar Singh

Proceedings of the 2020 International Conference on COMmunication Systems & NETworkS, 2020

2019

Improvement in Retention Time of Capacitorless DRAM with Access Transistor.

Md. Hasan Raza Ansari, Jawar Singh

CoRR, 2019

Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks.

Alok Kumar Kamal, Jawar Singh

CoRR, 2019

Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications.

Ankit Sirohi, Chitrakant Sahu, Jawar Singh

IEEE Access, 2019

2017

Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET.

Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function.

Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

SiGe Source Charge Plasma TFET for Biosensing Applications.

Nawaz Shafi, Chitrakant Sahu, C. Periasamy, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016

Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function.

Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors.

Meena Panchore, Jawar Singh, Saraju P. Mohanty, Elias Kougianos

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Proposal of Heterogate Technique for Performance Enhancement of DM-TFET.

Chaitanya Maradana, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule.

Muhammad Khalid, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015

A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process.

Sunil Kumar Pandey, Jawar Singh

Microelectron. J., 2015

Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k.

Kanchan Cecil, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Extended Base Schottky-Collector Bipolar Charge Plasma Transistor.

Lokesh Kumar Bramhane, Jawar Singh

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization.

Deep Kishore Parsediya, Jawar Singh, Pavan Kumar Kankar

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Linearly separable pattern classification using memristive crossbar circuits.

Komal Singh, Chitrakant Sahu, Jawar Singh

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Dual-sided doped memristor and it's SPICE modelling for improved electrical properties.

Anup Shrivastava, Jawar Singh

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Realization of efficient RF energy harvesting circuits employing different matching technique.

Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Manoj Singh Parihar

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

A highly reliable NBTI Resilient 6T SRAM cell.

Jawar Singh, Narayanan Vijaykrishnan

Microelectron. Reliab., 2013

An Efficient RF Energy Harvester with Tuned Matching Circuit.

Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Pravin Neminath Kondekar

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Dual sided doped memristor and it's mathematical modelling.

Anup Shrivastava, Jawar Singh

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.

Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan

Integr., 2012

Process variation tolerant 9T SRAM bitcell design.

G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2010

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.

Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Investigating the impact of NBTI on different power saving cache strategies.

Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan

Proceedings of the Design, Automation and Test in Europe, 2010

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V_<i>DD</i> applications.

Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Robust power aware SRAM bitcell designs.

Jawar Singh

PhD thesis, 2009

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.

Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Single ended 6T SRAM with isolated read-port for low-power embedded systems.

Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A single ended 6T SRAM cell design for ultra-low-voltage applications.

Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty

IEICE Electron. Express, 2008

Pseudo parallel architecture for AES with error correction.

Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Failure analysis for ultra low power nano-CMOS SRAM under process variations.

Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.

Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A nano-CMOS process variation induced read failure tolerant SRAM cell.

Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault tolerant bit parallel finite field multipliers using LDPC codes.

Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fault Tolerant Reversible Finite Field Arithmetic Circuits.

Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007

Single Event Upset Detection and Correction.

Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan

Proceedings of the 10th International Conference on Information Technology, 2007

A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards.

Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew

Proceedings of the 10th International Conference on Information Technology, 2007