Javier Zalamea

According to our database, Javier Zalamea authored at least 11 papers between 2000 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Power-efficient VLIW design using clustering and widening.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Int. J. Embed. Syst., 2008

2004

Register Constrained Modulo Scheduling.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

IEEE Trans. Parallel Distributed Syst., 2004

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Int. J. Parallel Program., 2004

High-performance and low-power VLIW cores for numerical computations.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Int. J. High Perform. Comput. Netw., 2004

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Proceedings of the Computer Systems: Architectures, 2004

2003

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero

Proceedings of the High Performance Computing, 5th International Symposium, 2003

Hierarchical Clustered Register File Organization for VLIW Processors.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2001

Modulo scheduling with integrated register spilling for clustered VLIW architectures.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

<i>MIRS</i>: Modulo Scheduling with Integrated Register Spilling.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the Languages and Compilers for Parallel Computing, 2001

2000

Improved spill code generation for software pipelined loops.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2000

Two-level hierarchical register file organization for VLIW processors.

Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000