Javier Valls-Coquillat

Mehdi Mhalla

Valentin Savin

Proceedings of the 12th International Symposium on Topics in Coding, 2023

2021

Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes.

[BibT_eX]

[DOI]

Nithin Raveendran

Bane Vasic

IEEE Access, 2021

2019

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

Francisco Miguel Garcia-Herrero

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems.

[BibT_eX]

[DOI]

Julián S. Bruno

Vicenç Almenar

Microprocess. Microsystems, 2019

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.

[BibT_eX]

[DOI]

Gabriele Perrone

Circuits Syst. Signal Process., 2019

Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes.

[BibT_eX]

[DOI]

J. M. Català-Pérez

Circuits Syst. Signal Process., 2019

2018

Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach.

[BibT_eX]

[DOI]

Proceedings of the 2018 20th International Conference on Transparent Optical Networks (ICTON), 2018

High-Throughput One-Channel RS(255, 239) Decoder.

[BibT_eX]

[DOI]

Gabriele Perrone

Francisco Miguel Garcia-Herrero

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks].

[BibT_eX]

[DOI]

Richard G. Lyons

IEEE Signal Process. Mag., 2017

2016

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

High-Performance NB-LDPC Decoder With Reduction of Message Exchange.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser.

[BibT_eX]

[DOI]

JOCN, 2015

A 630 Mbps non-binary LDPC decoder for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

Erbao Li

IEEE Trans. Very Large Scale Integr. Syst., 2014

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain.

[BibT_eX]

[DOI]

Guillermo A. Jaquenod

Javier Siman

Int. J. Reconfigurable Comput., 2014

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2014

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree.

[BibT_eX]

[DOI]

J. M. Català-Pérez

K. Liu

Shu Lin

IEEE Commun. Lett., 2014

A symbol flipping decoder for NB-LDPC relying on multiple votes.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

2013

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2013

High-speed NB-LDPC decoder for wireless applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

Low latency T-EMS decoder for non-binary LDPC codes.

[BibT_eX]

[DOI]

Erbao Li

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes.

[BibT_eX]

[DOI]

Fabian Angarita

J. Signal Process. Syst., 2012

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.

[BibT_eX]

[DOI]

Pramod Kumar Meher

IEEE Trans. Very Large Scale Integr. Syst., 2012

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

FPGA implementation of an OFDM-based WLAN receiver.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation.

[BibT_eX]

[DOI]

IET Commun., 2012

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.

[BibT_eX]

[DOI]

Mark F. Flanagan

IEEE Commun. Lett., 2012

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Decoder for an enhanced serial generalized bit flipping algorithm.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High-throughput FPGA-based emulator for structured LDPC codes.

[BibT_eX]

[DOI]

Fabian Angarita

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Low Cost Hardware Implementation of Logarithm Approximation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

High-Speed RS(255, 239) Decoder Based on LCC Decoding.

[BibT_eX]

[DOI]

Pramod Kumar Meher

Circuits Syst. Signal Process., 2011

2010

FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

2009

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

50 Years of CORDIC: Algorithms, Architectures, and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2009

FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices.

[BibT_eX]

[DOI]

IEEE Trans. Educ., 2007

Time Synchronization for the IEEE 802.11a/g WLAN Standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE 18th International Symposium on Personal, 2007

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN.

[BibT_eX]

[DOI]

Fabian Angarita Preciado

Trinidad Sansaloni Balaguer

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard.

[BibT_eX]

[DOI]

Proceedings of the 15th European Signal Processing Conference, 2007

Design of an efficient digital down-converter for a SDR-based DVB-S receiver.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

The use of CORDIC in software defined radios: a tutorial.

[BibT_eX]

[DOI]

Vicenç Almenar

IEEE Commun. Mag., 2006

Design of high performance timing recovery loops for communication applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005

Statistical Power Estimation for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Performance evaluation of fine time synchronizers for WLANs.

[BibT_eX]

[DOI]

Proceedings of the 13th European Signal Processing Conference, 2005

2004

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Personal, 2004

Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2.

[BibT_eX]

[DOI]

Felip Vicedo

Eduardo R. de Lima

Proceedings of the Field Programmable Logic and Application, 2004

Power analysis and estimation tool integrated with XPOWER.

[BibT_eX]

[DOI]

Elias Todorovich

Eduardo I. Boemo

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

Digit-Serial Complex-Number Multipliers on FPGAs.

[BibT_eX]

[DOI]

Keshab K. Parhi

J. VLSI Signal Process., 2003

Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers.

[BibT_eX]

[DOI]

Eduardo I. Boemo

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.

[BibT_eX]

[DOI]

José Marín-Roig

Fabian Angarita

Felip Vicedo

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

Evaluation of CORDIC Algorithms for FPGA Design.

[BibT_eX]

[DOI]

Martin Kuhlmann

Keshab K. Parhi

J. VLSI Signal Process., 2002

FPGA-based radix-4 butterflies for HIPERLAN/2.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

High Performance Quadrature Digital Mixers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Distributed arithmetic radix-2 butterflies for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

FPGA based on-line complex-number multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

FPGA-based digit-serial complex number multiplier-accumulator.

[BibT_eX]

[DOI]

Keshab K. Parhi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Fast FPGA-based pipelined digit-serial/parallel multipliers.

[BibT_eX]

[DOI]

Trini Sansaloni

Marcos Martínez-Peiró

Eduardo I. Boemo

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Efficient complex-number multipliers mapped on FPGA.

[BibT_eX]

[DOI]