Javier J. Sieiro
Orcid: 0000-0001-9545-5347
According to our database1,
Javier J. Sieiro
authored at least 13 papers
between 2009 and 2020.
Collaborative distances:
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Bibliography
2020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access, 2020
2019
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.
Integr., 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
2017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
2016
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques.
Integr., 2016
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2010
Integr., 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009