Javier Hormigo

Alberto A. Del Barrio

Guillermo Botella

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.

[BibT_eX]

[DOI]

Marco Hormigo-Jiménez

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

High-Radix Formats for Enhancing Floating-Point FPGA Implementations.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2022

2021

Efficient Floating-Point Givens Rotation Unit.

[BibT_eX]

[DOI]

Sergio D. Muñoz

Circuits Syst. Signal Process., 2021

FPGA acceleration of bit-true simulations for word-length optimization.

[BibT_eX]

[DOI]

Gabriel Caffarena

Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

2020

New Results on Non-Normalized Floating-Point Formats.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Floating-Point Fused Multiply-Add under HUB Format.

[BibT_eX]

[DOI]

Sonia Gonzalez-Navarro

Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019

Fast HUB Floating-Point Adder for FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden.

[BibT_eX]

[DOI]

Andrés Rodríguez

Rev. Iberoam. de Tecnol. del Aprendiz., 2019

Reproducible Summation Under HUB Format.

[BibT_eX]

[DOI]

Francisco J. Jaime

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

Unbiased Rounding for HUB Floating-Point Addition.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

2017

HUB Floating Point for Improving FPGA Implementations of DSP Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Introduction to the Special Issue on Computer Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Floating Point Square Root under HUB Format.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

New Formats for Computing with Real-Numbers under Round-to-Nearest.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2015

High-Throughput FPGA Implementation of QR Decomposition.

[BibT_eX]

[DOI]

Sergio D. Muñoz

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Improving fixed-point implementation of QR decomposition by rounding-to-nearest.

[BibT_eX]

[DOI]

Sergio D. Muñoz

Proceedings of the International Symposium on Consumer Electronics, 2015

Simplified floating-point units for high dynamic range image and video systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Consumer Electronics, 2015

2014

Optimizing DSP circuits by a new family of arithmetic operators.

[BibT_eX]

[DOI]

Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013

Self-Reconfigurable Constant Multiplier for FPGA.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

Multioperand Redundant Adders on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Efficient floating-point representation for balanced codes for FPGA devices.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Radix-2 Multioperand and Multiformat Streaming Online Addition.

[BibT_eX]

[DOI]

Tomás Lang

IEEE Trans. Computers, 2012

A study of decimal left shifters for binary numbers.

[BibT_eX]

[DOI]

Carlos Diego Moreno-Moreno

Michael J. Schulte

Inf. Comput., 2012

2011

High-Speed Algorithms and Architectures for Range Reduction Computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers.

[BibT_eX]

[DOI]

Proceedings of the IT Revolutions, 2011

2010

Enhanced Scaling-Free CORDIC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

CORDIC-based LMMSE equalizer for Software Defined Radio.

[BibT_eX]

[DOI]

Murugappan Senthilvelan

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

UCORE: Reconfigurable Platform for Educational Purposes.

[BibT_eX]

[DOI]

Francisco J. Quiles

Manuel Ortiz

María Brox

Carlos Diego Moreno-Moreno

Carlos Diego Moreno-Moreno

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

2009

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Efficient Implementation of Carry-Save Adders in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

Pipelined Architecture for Additive Range Reduction.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

New SIMD instructions set for image processing applications enhancement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

SIMD Enhancements for a Hough Transform Implementation.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Improving the Throughput of On-line Addition for Data Streams.

[BibT_eX]

[DOI]

Tomás Lang

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

SAD computation based on online arithmetic for motion estimation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Pipelined Range Reduction for Floating Point Numbers.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

On-line Multioperand Addition Based on On-line Full Adders.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

CORDIC Processor for Variable-Precision Interval Arithmetic.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2004

Evaluation of Elementary Functions Using Multimedia Features.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

2003

Texture segmentation and analysis using local spectral methods.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

2002

Polynomial Evaluation on Multimedia Processors.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000

MMX-Like Architecture Extension to Support the Rotation Operation.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

A Hardware Algorithm for Variable-Precision Logarithm.

[BibT_eX]

[DOI]

Michael J. Schulte

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Texture segmentation through eigen-analysis of the Pseudo-Wigner distribution.

[BibT_eX]

[DOI]

Gabriel Cristóbal

Pattern Recognit. Lett., 1999

Arithmetic Unit for the Computation of Interval Elementary Functions.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998

High resolution spectral analysis of images using the pseudo-Wigner distribution.

[BibT_eX]

[DOI]

Gabriel Cristóbal

IEEE Trans. Signal Process., 1998

A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions.

[BibT_eX]

[DOI]