Javier D. Bruguera

IEEE Trans. Computers, 2011

Guest Editors' Introduction: Special Section on Computer Arithmetic.

[BibT_eX]

[DOI]

Marius Cornea

Debjit Das Sarma

IEEE Trans. Computers, 2011

Composite Iterative Algorithm and Architecture for q-th Root Calculation.

[BibT_eX]

[DOI]

Álvaro Vázquez

Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2009

High Performance Image Processing on a Massively Parallel Processor Array.

[BibT_eX]

[DOI]

Cesar Diaz-Resco

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

A Radix-2 Digit-by-Digit Architecture for Cube Root.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Topic 10: Parallel Numerical Algorithms.

[BibT_eX]

[DOI]

Hans-Joachim Bungartz

Peter Arbenz

Bruce Hendrickson

Proceedings of the Euro-Par 2008, 2008

A New Rounding Algorithm for Variable Latency Division and Square Root Implementations.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

An FPGA architecture for CABAC decoding in manycore systems.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Forcing one-sided results in Goldschmidt algorithm.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

A Digit-by-Digit Algorithm for mth Root Extraction.

[BibT_eX]

[DOI]

Paolo Montuschi

Luigi Ciminiera

IEEE Trans. Computers, 2007

Hardware support for adaptive tessellation of Bézier surfaces based on local tests.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Entropy Coding on a Programmable Processor Array for Multimedia SoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

High-Throughput Architecture for H.264/AVC CABAC Compression System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2006

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.

[BibT_eX]

[DOI]

Viay Holimath

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

High-Speed Function Approximation Using a Minimax Quadratic Interpolator.

[BibT_eX]

[DOI]

Stuart F. Oberman

Jean-Michel Muller

IEEE Trans. Computers, 2005

Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps.

[BibT_eX]

Proceedings of the 13-th International Conference in Central Europe on Computer Graphics, 2005

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

Algorithm and Architecture for Logarithm, Exponential, and Powering Computation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Floating-Point Multiply-Add-Fused with Reduced Latency.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Algorithms and Hardware for Data Compression in Point Rendering Applications.

[BibT_eX]

Proceedings of the 12-th International Conference in Central Europe on Computer Graphics, 2004

Arithmetic Coding Architecture for H.264/AVC CABAC Compression System.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

Multilevel Reverse-Carry Addition: Single and Dual Adders.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2003

High performance air pollution modeling for a power plant environment.

[BibT_eX]

[DOI]

Parallel Comput., 2003

Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

Research Article: A GIS-embedded system to support land consolidation plans in Galicia.

[BibT_eX]

[DOI]

Int. J. Geogr. Inf. Sci., 2003

Adaptive Tessellation of NURBS Surfaces.

[BibT_eX]

[DOI]

Proceedings of the 11-th International Conference in Central Europe on Computer Graphics, 2003

On-line high-radix exponential with selection by rounding.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

High-Radix Iterative Algorithm for Powering Computation.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Floating-Point Fused Multiply-Add with Reduced Latency.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Hardware Implementation of the Subdivision Loop Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, 2002

High-Radix Logarithm with Selection by Rounding.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on 3D Data Processing Visualization and Transmission (3DPVT 2002), 2002

2001

Multilevel reverse most-significant carry computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

The STEM-II Air Quality Model on a Distributed Memory System.

[BibT_eX]

[DOI]

Proceedings of the 30th International Workshops on Parallel Processing (ICPP 2001 Workshops), 2001

Parallelization of the STEM-II Air Quality Model.

[BibT_eX]

[DOI]

Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001

COPA: a GIS-based Tool for Land Consolidation Projects.

[BibT_eX]

[DOI]

Proceedings of the ACM-GIS 2001, 2001

Implementation of a NURBS to Bézier Conversor with Constant Latency.

[BibT_eX]

[DOI]

Paula N. Mallón

Proceedings of the Field-Programmable Logic and Applications, 2001

FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation.

[BibT_eX]

[DOI]

Jean-Michel Muller

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree.

[BibT_eX]

[DOI]

Jean-Michel Muller

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

Very-High Radix CORDIC Rotation Based on Selection by Rounding.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2000

Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

VLSI systolic array architecture for the lattice structure of the discrete wavelet transform.

[BibT_eX]

[DOI]

Carlos E. Cabrera Reyes

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Multilevel Reverse-Carry Adder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Architectures for arithmetic coding in image compression.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

Parallel Architecture for Conversion of NURBS Curves to Bézier Curves.

[BibT_eX]

[DOI]

Paula N. Mallón

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999

Leading-One Prediction with Concurrent Position Correction.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

New model for arithmetic coding/decoding of multilevel images based on a cache memory.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998

Radix-4 Vectoring CORDIC Algorithm and Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1998

A novel design of a two operand normalization circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Leading-one prediction scheme for latency improvement in single datapath floating-point adders.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1997

High-performance VLSI architecture for the Viterbi algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 1997

High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

VLSI implementation of an area-efficient architecture for the Viterbi algorithm.

[BibT_eX]

[DOI]

Carlos Cabrera

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

A VLSI implementation of an arithmetic coder for image compression.

[BibT_eX]

[DOI]

Mercedes Peón

Proceedings of the 23rd EUROMICRO Conference '97, 1997

New arithmetic coder/decoder architectures based on pipelining.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

Cordic based parallel/pipelined architecture for the Hough transform.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

Unified Mixed Radix 2-4 Redundant CORDIC Processor.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

High performance VLSI architecture for the trellis coded quantization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

High Radix Cordic Rotation Based on Selection by Rounding.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '96 Parallel Processing, 1996

Radix-4 Vectoring Cordic Algorithm And Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995

A Parallel Architecture for the Self-Sorting FFT Algorithm.

[BibT_eX]

[DOI]

Francisco Argüello

J. Parallel Distributed Comput., 1995

2-D DCT using on-line arithmetic.

[BibT_eX]

[DOI]

José Antonio Hidalgo López

Proceedings of the 1995 International Conference on Acoustics, 1995

CORDIC Architectures with Parallel Compensation of the Scale Factor.

[BibT_eX]

[DOI]

Julio Villalba

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Digit On-line Large Radix CORDIC Rotator.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Redundant CORDIC Rotator Based on Parallel Prediction.

[BibT_eX]

[DOI]

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

Parallel Architecture for Fast Transforms with Trigonometric Kernel.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1994

1993

Design of a Pipelined Radix 4 CORDIC Processor.

[BibT_eX]

[DOI]

Juan Julián Merelo Guervós

Parallel Comput., 1993

1992

Image reconstruction on hypercube computers: Application to electron microscopy.

[BibT_eX]

[DOI]

Signal Process., 1992

1991

Design of a constant geometry fast Hartley transformer.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Conference on Acoustics, 1991

1990

Gaussian elimination with pivoting on hypercubes.

[BibT_eX]

[DOI]

Parallel Comput., 1990

Parallel quadrant interlocking factorization on hypercube computers.

[BibT_eX]

[DOI]

Inmaculada García

Parallel Comput., 1990

Multidimensional fast Hartley transform onto SIMD hypercubes.

[BibT_eX]

[DOI]

Francisco Fernandez Rivera

Francisco Argüello

Microprocessing and Microprogramming, 1990

A reliability model for multiprocessor networks with degradable nodes.

[BibT_eX]

[DOI]