Javad Talafy

According to our database, Javad Talafy authored at least 5 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit.

Saeed Seyedfaraji, Javad Talafy, Mohamed M. Sabry, Semeen Rehman

CoRR, 2022

2021

A High Performance, Multi-Bit Output Logic-in-Memory Adder.

Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh

IEEE Trans. Emerg. Top. Comput., 2021

2020

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories.

Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi

Microprocess. Microsystems, 2020

2018

DUSTER: DUal Source Write TERmination Method for STT-RAM Memories.

Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution.

Javad Talafy, Hamid R. Zarandi

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017