Jaushin Lee

According to our database, Jaushin Lee authored at least 14 papers between 1991 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

Hierarchical test generation under architectural level functional constraints.

Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1994

Architectural level test generation for microprocessors.

Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Addressing design for testability at the architectural level.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

An architectural level test generator based on nonlinear equation solving.

Jaushin Lee, Janak H. Patel

J. Electron. Test., 1993

Testability analysis based on structural and behavioral information.

Jaushin Lee, Janak H. Patel

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Impact of high level functional constraints on testability.

Jaushin Lee, Vivek Chickermane, Janak H. Patel

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992

Architectural Level Test Generation and Fault Simulation

Jaushin Lee

PhD thesis, 1992

An Instruction Sequence Assembling Methodology for Testing Microprocessors.

Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Design for Testability Using Architectural Descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A comparative study of design for testability methods using high-level and gate-level descriptions.

Vivek Chickermane, Jaushin Lee, Janak H. Patel

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Hierarchical Test Generation under Intensive Global Functional Constraints.

Jaushin Lee, Janak H. Patel

Proceedings of the 29th Design Automation Conference, 1992

1991

ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults.

Jaushin Lee, Janak H. Patel

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation.

Jaushin Lee, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Architectural Level Test Generator for a Hierarchical Design Environment.

Jaushin Lee, Janak H. Patel

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991