Jaume Segura

Roberto Gómez-Fuentes

Fabian Vargas

J. Electron. Test., February, 2024

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.

[BibT_eX]

[DOI]

CoRR, 2024

A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications.

[BibT_eX]

[DOI]

IEEE Access, 2024

2023

A Compact Double-Exponential Circuit for Single Event Transient Emulation.

[BibT_eX]

[DOI]

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022

2020

Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing.

[BibT_eX]

[DOI]

Sensors, 2020

2019

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors.

[BibT_eX]

[DOI]

Gabriel Torrens

Cristian Carmona

Daniel Malagón-Periánez

María del Carmen Jiménez-Ramos

IEEE Trans. Emerg. Top. Comput., 2019

2018

Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators.

[BibT_eX]

[DOI]

Sensors, 2018

Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources.

[BibT_eX]

[DOI]

Carlos Guerrero Sanchez

Javier García López

José Luis Merino

Microelectron. Reliab., 2017

Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.

[BibT_eX]

[DOI]

Javier Martín-Martínez

Proceedings of the 14th International Conference on Synthesis, 2017

Integrated microelectromechanical systems in the More than Moore era.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Cantilever NEMS relay-based SRAM devices for enhanced reliability.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective.

[BibT_eX]

[DOI]

Commun. Nonlinear Sci. Numer. Simul., 2016

2015

Low V<sub>DD</sub> and body bias conditions for testing bridge defects in the presence of process variations.

[BibT_eX]

[DOI]

Jose Luis Garcia-Gervacio

Microelectron. J., 2015

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

2014

Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Analysis of fin height on FinFET SRAM cell hardening.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Alternate characterization technique for static random-access memory static noise margin determination.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2013

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias.

[BibT_eX]

[DOI]

Jose Luis Garcia-Gervacio

Jaime Martínez-Castillo

Proceedings of the 14th Latin American Test Workshop, 2013

2012

Resistive bridge defect detection enhancement under parameter variations combining Low V<sub>DD</sub> and body bias in a delay based test.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Testing of Stuck-Open Faults in Nanometer Technologies.

[BibT_eX]

[DOI]

Julio Vazquez Hernandez

IEEE Des. Test Comput., 2012

2011

8T vs. 6T SRAM cell radiation robustness: A comparative analysis.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Reliability analysis of small delay defects in vias located in signal paths.

[BibT_eX]

[DOI]

Proceedings of the 11th Latin American Test Workshop, 2010

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Stuck-Open Fault Leakage and Testing in Nanometer Technologies.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A modern look at the CMOS stuck-open fault.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

2008

Using stochastic logic for efficient pattern recognition analysis.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2008

2007

Charge-based testing BIST for embedded memories.

[BibT_eX]

[DOI]

Ivan de Paúl

IET Comput. Digit. Tech., 2007

Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment.

[BibT_eX]

[DOI]

X. Cano

Ricardo Graciani Diaz

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Impact of Thermal Gradients on Clock Skew and Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2006

Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Leakage Power Characterization Considering Process Variations.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Fully CMOS Low-Cost Chaotic Neural Network.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2006

CMOS Testing at the End of the Roadmap: Challenges and Opportunities.

[BibT_eX]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A compact model to identify delay faults due to crosstalk.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A compact gate-level energy and delay model of dynamic CMOS gates.

[BibT_eX]

[DOI]

Carol de Benito

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Compact Static Power Model of Complex CMOS Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

The anatomy of nanometer timing failures.

[BibT_eX]

[DOI]

Chuck Hawkins

Proceedings of the 10th European Test Symposium, 2005

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

An analytical charge-based compact delay model for submicrometer CMOS inverters.

[BibT_eX]

[DOI]

Jaume A. Segura

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A Two-Level Power-Grid Model for Transient Current Testing Evaluation.

[BibT_eX]

[DOI]

Vincent Canals

J. Electron. Test., 2004

Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A BIST-based Charge Analysis for Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

A BICS for CMOS OpAmps by Monitoring the Supply Current Peak.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Structural RFIC device testing through built-in thermal monitoring.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2003

A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect.

[BibT_eX]

[DOI]

Charles F. Hawkins

Ali Keshavarzi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

CMOS IC nanometer technology failure mechanisms.

[BibT_eX]

[DOI]

Charles F. Hawkins

Ali Keshavarzi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era.

[BibT_eX]

[DOI]

Peter C. Maxwell

IEEE Des. Test Comput., 2002

Challenges in Nanometric Technology Scaling: Trends and Projections.

[BibT_eX]

[DOI]

Vivek De

Ali Keshavarzi

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Parametric Failures in CMOS ICs - A Defect-Based Analysis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

GHz Testing and Its Fuzzy Targets.

[BibT_eX]

Chuck Hawkins

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A BICS for CMOS Opamps by Monitoring the Supply Current Peak.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

An Off-Chip Sensor Circuit for On-Line Transient Current Testing.

[BibT_eX]

[DOI]

André Ivanov

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A novel wavelet transform based transient current analysis for fault detection and localization.

[BibT_eX]

[DOI]

Swarup Bhunia

Kaushik Roy

Proceedings of the 39th Design Automation Conference, 2002

2001

Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Experimental Results on BIC Sensors for Transient Current Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Transient Current Monitoring Using a Current-to-Frequency Converter.

[BibT_eX]

Proceedings of the 1st Latin American Test Workshop, 2000

On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999

Test and Reliability: Partners in IC Manufacturing, Part 2.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1999

Test and Reliability: Partners in IC Manufacturing, Part 1.

[BibT_eX]

[DOI]

Charles F. Hawkins

IEEE Des. Test Comput., 1999

Analyzing the Need for ATPG Targeting GOS Defects.

[BibT_eX]

[DOI]

Eugeni Isern

Miquel Roca

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998

A variable threshold voltage inverter for CMOS programmable logic circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

Clocked Dosimeter Compatible with Digital CMOS Technology.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Integrated Cmos Linear Dosimeter.

[BibT_eX]

[DOI]

Oscar Calvo

M. González

C. Romero

Eugeni Isern

Miquel Roca

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

1997

A detailed analysis of CMOS SRAM's with gate oxide short defects.

[BibT_eX]

[DOI]

Antonio Rubio

IEEE J. Solid State Circuits, 1997

1996

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.

[BibT_eX]

[DOI]

J. Electron. Test., 1996

1995

An approach to dynamic power consumption current testing of CMOS ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A built-in quiescent current monitor for CMOS VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1992

Quiescent current analysis and experimentation of defective CMOS circuits.

[BibT_eX]

[DOI]

Jaume A. Segura