Jaswanth Sreeram

According to our database, Jaswanth Sreeram authored at least 14 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Are Web Applications Ready for Parallelism?

Cosmin Radoi, Stephan Herhut, Jaswanth Sreeram, Danny Dig

Proceedings of the 50th Hawaii International Conference on System Sciences, 2017

2013

Parallel JavaScript: bringing the compute power of multi-core CPUs and GPUs to the world of web graphics.

Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram

Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2013

River trail: a path to parallelism in JavaScript.

Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram

Proceedings of the 2013 ACM SIGPLAN International Conference on Object Oriented Programming Systems Languages & Applications, 2013

2012

Safe compiler-driven transaction checkpointing and recovery.

Jaswanth Sreeram, Santosh Pande

Proceedings of the 27th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2012

Hybrid Transactions: Lock Allocation and Assignment for Irrevocability.

Jaswanth Sreeram, Santosh Pande

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Parallel Programming for the Web.

Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram

Proceedings of the 4th USENIX Workshop on Hot Topics in Parallelism, 2012

2011

Optimistic semantic synchronization.

Jaswanth Sreeram

PhD thesis, 2011

Enriching 3-D Video Games on Multicores.

Romain Cledat, Tushar Kumar, Jaswanth Sreeram, Santosh Pande

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Parallelizing a Real-Time Physics Engine Using Transactional Memory.

Jaswanth Sreeram, Santosh Pande

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010

Exploiting approximate value locality for data synchronization on multi-core processors.

Jaswanth Sreeram, Santosh Pande

Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

2008

Statistically Analyzing Execution Variance for Soft Real-Time Applications.

Tushar Kumar, Romain Cledat, Jaswanth Sreeram, Santosh Pande

Proceedings of the Languages and Compilers for Parallel Computing, 2008

2007

A profile-driven statistical analysis framework for the design optimization of soft real-time applications.

Tushar Kumar, Jaswanth Sreeram, Romain Cledat, Santosh Pande

Proceedings of the 6th joint meeting of the European Software Engineering Conference and the ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2007

RSTM : A Relaxed Consistency Software Transactional Memory for Multicores.

Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Data trace cache: an application specific cache architecture.

Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, Krishna V. Palem

SIGARCH Comput. Archit. News, 2006