Jason Hibbeler
According to our database1,
Jason Hibbeler
authored at least 8 papers
between 1997 and 2015.
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Bibliography
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
2014
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2010
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Technology migration technique for designs with strong RET-driven layout restrictions.
Proceedings of the 2005 International Symposium on Physical Design, 2005
1997