Jason Cong

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Towards layout-friendly high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Transformation from ad hoc EDA to algorithmic EDA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Energy-efficient scheduling on heterogeneous multi-core architectures.

[BibT_eX]

[DOI]

Bo Yuan

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

CHARM: a composable heterogeneous accelerator-rich microprocessor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Static and dynamic co-optimizations for blocks mapping in hybrid caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Memory partitioning and scheduling co-optimization in behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only).

[BibT_eX]

[DOI]

Bingjun Xiao

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

FPGA-accelerated 3D reconstruction using compressive sensing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Combining module selection and replication for throughput-driven streaming programs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis.

[BibT_eX]

[DOI]

Peng Zhang

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A metric for layout-friendly microarchitecture optimization in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Architecture support for accelerator-rich CMPs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

An integrated and automated memory optimization flow for FPGA behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Compilation and architecture support for customized vector instruction extension.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Platform characterization for Domain-Specific Computing.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Automatic memory partitioning and scheduling for throughput and power optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

High-Level Synthesis for FPGAs: From Prototyping to Deployment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pattern-Mining for Behavioral Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Overview of Center for Domain-Specific Computing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2011

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Customizable Domain-Specific Computing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications.

[BibT_eX]

[DOI]

Muhuan Huang

Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration.

[BibT_eX]

[DOI]

Bingjun Xiao

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Visual Computing - 7th International Symposium, 2011

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

An energy-efficient adaptive hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A unified optimization framework for simultaneous gate sizing and placement under density constraints.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

The DIMM tree architecture: A high bandwidth and scalable memory system.

[BibT_eX]

[DOI]

Kanit Therdsteerasukdi

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Combined loop transformation and hierarchy allocation for data reuse optimization.

[BibT_eX]

[DOI]

Peng Zhang

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

ATree-based topology synthesis for on-chip network.

[BibT_eX]

[DOI]

Yuhui Huang

Bo Yuan

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Assuring application-level correctness against soft errors.

[BibT_eX]

[DOI]

Karthik Gururaj

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms.

[BibT_eX]

[DOI]

Muhuan Huang

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Resolving implicit barrier synchronizations in FPGA HLS (abstract only).

[BibT_eX]

[DOI]

Alexandros Papakonstantinou

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Multilevel Granularity Parallelism Synthesis on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Thermal-aware cell and through-silicon-via co-placement for 3D ICs.

[BibT_eX]

[DOI]

Yiyu Shi

Proceedings of the 48th Design Automation Conference, 2011

A reuse-aware prefetching scheme for scratchpad memory.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support.

[BibT_eX]

[DOI]

Yu-Ting Chen

Glenn Reinman

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Accelerating vision and navigation applications on a customizable platform.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Domain-specific processor with 3D integration for medical image processing.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Era of customization and specialization.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

RF-Interconnect for Future Network-On-Chip.

[BibT_eX]

[DOI]

Sai-Wang Tam

Eran Socher

Glenn D. Reinman

Proceedings of the Low Power Networks-on-Chip., 2011

2010

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Evaluating Statistical Power Optimization.

[BibT_eX]

[DOI]

Puneet Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Advances and Challenges in 3D Physical Design.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

NSF Workshop on EDA: Past, Present, and Future (Part 2).

[BibT_eX]

[DOI]

Robert K. Brayton

IEEE Des. Test Comput., 2010

NSF Workshop on EDA: Past, Present, and Future (Part 1).

[BibT_eX]

[DOI]

Robert K. Brayton

IEEE Des. Test Comput., 2010

An analytical placer for mixed-size 3D placement.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Bit-level optimization for high-level synthesis and FPGA-based acceleration.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

LUT-based FPGA technology mapping for reliability (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Accelerating Monte Carlo based SSTA using FPGA.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Comparative Study on the Architecture Templates for Dynamic Nested Loops.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Coordinated resource optimization in behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

LUT-based FPGA technology mapping for reliability.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.

[BibT_eX]

[DOI]

Chunyue Liu

Glenn Reinman

Proceedings of the 47th Design Automation Conference, 2010

Logic-on-logic 3D integration and placement.

[BibT_eX]

[DOI]

Thorlindur Thorolfsson

Paul D. Franzon

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Synthesis Algorithm for Application-Specific Homogeneous Processor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2009

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

The Last Byte: The HLS tipping point.

[BibT_eX]

[DOI]

Wolfgang Rosenstiel

IEEE Des. Test Comput., 2009

Multiband RF-interconnect for reconfigurable network-on-chip communications.

[BibT_eX]

[DOI]

Alexandros Papakonstantinou

Glenn Reinman

Sai-Wang Tam

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

A scalable micro wireless interconnect structure for CMPs.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual International Conference on Mobile Computing and Networking, 2009

Behavior-level observability don't-cares and application to low-power behavioral synthesis.

[BibT_eX]

[DOI]

Alexandros Papakonstantinou

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

High-performance CUDA kernel execution on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 23rd international conference on Supercomputing, 2009

Parallel multi-level analytical global placement on graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Scheduling with soft constraints.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A rigorous framework for convergent net weighting schemes in timing-driven placement.

[BibT_eX]

[DOI]

Tony F. Chan

Eric Radke

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Customizable domain-specific computing.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Revisiting bitwidth optimizations.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Synthesis of reconfigurable high-performance multicore systems.

[BibT_eX]

[DOI]

Karthik Gururaj

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

Energy efficient multiprocessor task scheduling under input-dependent variation.

[BibT_eX]

[DOI]

Karthik Gururaj

Proceedings of the Design, Automation and Test in Europe, 2009

From milliwatts to megawatts: system level power challenge.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Moore's Law: another casualty of the financial meltdown?

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

A variation-tolerant scheduler for better than worst-case behavioral synthesis.

[BibT_eX]

[DOI]

Albert Liu

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A multilevel analytical placement for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

On the futility of statistical power optimization.

[BibT_eX]

[DOI]

Puneet Gupta

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Enhancing Placement with Multilevel Techniques.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

FPGA Technology Mapping.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

A Robust Mixed-Size Legalization and Detailed Placement Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Highly Efficient Gradient Computation for Density-Constrained Analytical Placement.

[BibT_eX]

[DOI]

Eric Radke

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Editorial: Special issue on 3D integrated circuits and microarchitectures.

[BibT_eX]

[DOI]

Yuan Xie

Paul D. Franzon

ACM J. Emerg. Technol. Comput. Syst., 2008

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

A new generation of C-base synthesis tool and domain-specific computing.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Power reduction of CMP communication networks via RF-interconnects.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Robust gate sizing via mean excess delay minimization.

[BibT_eX]

[DOI]

Lieven Vandenberghe

Proceedings of the 2008 International Symposium on Physical Design, 2008

Highly efficient gradient computation for density-constrained analytical placement methods.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

RF interconnects for communications on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

MC-Sim: an efficient simulation tool for MPSoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Fault tolerant placement and defect reconfiguration for nano-FPGAs.

[BibT_eX]

[DOI]

Amit Agarwal

Brian Tagiku

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

CMP network-on-chip overlaid with multi-band RF-interconnect.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Mapping for better than worst-case delays in LUT-based FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Lithographic aerial image simulation with FPGA-based hardwareacceleration.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Pattern-based behavior synthesis for FPGA resource reduction.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Simultaneous FU and Register Binding Based on Network Flow Method.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Scheduling with integer time budgeting for low-power optimization.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Large-Scale Global Placement.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Accelerating Sequential Applications on CMPs Using Core Spilling.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2007

Routability-Driven Placement and White Space Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Optimality Study of Logic Synthesis for LUT-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fine grain 3D integration for microarchitecture design through cube packing exploration.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Synthesis of an application-specific soft multiprocessor system.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-Aware 3D IC Placement Via Transformation.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Locality and Utilization in Placement Suboptimality.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Optimal simultaneous module and multivoltage assignment for low power.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Simultaneous placement with clustering and duplication.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Protecting Combinational Logic Synthesis Solutions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Fast floorplanning by look-ahead enabled recursive bipartitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

FPGA Design Automation: A Survey.

[BibT_eX]

[DOI]

Peichen Pan

Found. Trends Electron. Des. Autom., 2006

Platform-Based Behavior-Level and System-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

mPL6: enhanced multilevel mixed-size placement.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Platform-based resource binding using a distributed register-file microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Optimal simultaneous mapping and clustering for FPGA delay optimization.

[BibT_eX]

[DOI]

Joey Y. Lin

Proceedings of the 43rd Design Automation Conference, 2006

An efficient and versatile scheduling algorithm based on SDC formulation.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Behavior and communication co-optimization for systems with sequential communication media.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Optimality study of resource binding with multi-Vdds.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A robust detailed placement for mixed-size IC designs.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An automated design flow for 3D microarchitecture evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Large-scale circuit placement.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Technology mapping and architecture evalution for <i>k/m</i>-macrocell-based FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Power modeling and characteristics of field programmable gate arrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

MARS-a multilevel full-chip gridless routing system.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Multilevel generalized force-directed method for circuit placement.

[BibT_eX]

[DOI]

Tony F. Chan

Kenton Sze

Proceedings of the 2005 International Symposium on Physical Design, 2005

mPL6: a robust multilevel mixed-size placement engine.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Understanding the energy efficiency of SMT and CMP with multiclustering.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Lower-bound estimation for multi-bitwidth scheduling.

[BibT_eX]

[DOI]

Xu Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Thermal via planning for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Robust mixed-size placement under tight white-space constraints.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Architecture and compilation for data bandwidth improvement in configurable embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Instruction set extension with shadow registers for configurable processors.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Simultaneous timing-driven placement and duplication.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Microarchitecture evaluation with floorplanning and interconnect pipelining.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Thermal-driven multilevel routing for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Are we ready for system-level synthesis?

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Yoshi Watanabe

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Bitwidth-aware scheduling and binding in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Optimal module and voltage assignment for low-power.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Retiming-based timing analysis with an application to mincut-based global placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Edge separability-based circuit clustering with application to multilevel circuit partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Architecture and synthesis for on-chip multicycle communication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Optimality and scalability study of existing placement algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An area-optimality study of floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A thermal-driven floorplanning algorithm for 3D ICs.

[BibT_eX]

[DOI]

Jie Wei

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Simultaneous Timing Driven Clustering and Placement for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Application-specific instruction generation for configurable processor architectures.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Low-power technology mapping for FPGA architectures with dual supply voltages.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

What happened to ASIC?: Go (recon)figure?

[BibT_eX]

[DOI]

Christopher B. Reynolds

Chris Rowen

Ray Simar

Proceedings of the 41th Design Automation Conference, 2004

Architecture-level synthesis for automatic interconnect pipelining.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Performance-driven mapping for CPLD architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Multilevel global placement with congestion control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Optimality, scalability and stability study of partitioning and placement algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Architecture and synthesis for multi-cycle communication.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Low-power high-level synthesis for FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Gradual Relaxation Techniques with Applications to Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Optimality and Stability Study of Timing-Driven Placement Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Large-Scale Circuit Placement: Gap and Promise.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

An Enhanced Multilevel Algorithm for Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Architecture evaluation for power-efficient FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Multilevel global placement with retiming.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Microarchitecture evaluation with physical planning.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Architecture and synthesis for multi-cycle on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Multi-level placement for large-scale mixed-size IC designs.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Optimality and scalability study of existing placement algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

An interconnect energy model considering coupling effects.

[BibT_eX]

[DOI]

Taku Uchino

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Wire width planning for interconnect performance optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Enhanced SPFD Rewiring on Improving Rewiring Ability.

[BibT_eX]

Joey Y. Lin

Wangning Long

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Global clustering-based performance-driven circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of 2002 International Symposium on Physical Design, 2002

Timing closure based on physical hierarchy.

[BibT_eX]

[DOI]

Proceedings of 2002 International Symposium on Physical Design, 2002

Physical hierarchy generation with routing congestion control.

[BibT_eX]

[DOI]

Proceedings of 2002 International Symposium on Physical Design, 2002

An enhanced multilevel routing system.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A new enhanced SPFD rewiring algorithm.

[BibT_eX]

[DOI]

Joey Y. Lin

Wangning Long

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

SPFD-based global rewiring.

[BibT_eX]

[DOI]

Yizhou Lin

Wangning Long

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

Buffer block planning for interconnect planning and prediction.

[BibT_eX]

[DOI]

Tianming Kong

Z. D. Pan

IEEE Trans. Very Large Scale Integr. Syst., 2001

Interconnect performance estimation models for design planning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect layout optimization under higher order RLC model forMCM designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect sizing and spacing with consideration of couplingcapacitance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

DUNE-a multilayer gridless routing system.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Pseudopin assignment with crosstalk noise control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

An interconnect-centric design flow for nanometer technologies.

[BibT_eX]

[DOI]

Proc. IEEE, 2001

Multilevel Approach to Full-Chip Gridless Routing.

[BibT_eX]

[DOI]

Yan Zhang VI

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Simultaneous logic decomposition with technology mapping in FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Improved crosstalk modeling for noise constrained interconnect optimization.

[BibT_eX]

[DOI]

Prasanna V. Srinivas

Proceedings of ASP-DAC 2001, 2001

2000

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Performance-driven technology mapping for heterogeneous FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Via design rule consideration in multilayer maze routing algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Incremental physical design.

[BibT_eX]

[DOI]

Majid Sarrafzadeh

Proceedings of the 2000 International Symposium on Physical Design, 2000

DUNE: a multi-layer gridless routing system with wire planning.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Pseudo pin assignment with crosstalk noise control.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Incremental CAD.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Physical Planning with Retiming.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Multilevel Optimization for Large-Scale Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Synthesis for FPGAs with embedded memory blocks.

[BibT_eX]

[DOI]

Kenneth Yan

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Technology mapping for k/m-macrocell based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Routing tree construction under fixed buffer locations.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Performance driven multi-level and multiway partitioning with retiming.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Depth optimal incremental mapping for field programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Multi-way partitioning using bi-partition heuristics.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Performance driven multiway partitioning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Edge separability based circuit clustering with application to circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Optimal FPGA mapping and retiming with efficient initial state computation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An efficient approach to multilayer layer assignment with anapplication to via minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

VIA design rule consideration in multi-layer maze routing algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

Buffer block planning for interconnect-driven floorplanning.

[BibT_eX]

[DOI]

Tianming Kong

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An implicit connection graph maze routing algorithm for ECO routing.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Interconnect Estimation and Dlanning for Deep Submicron Designs.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization.

[BibT_eX]

[DOI]

Honching Li

Proceedings of the 36th Conference on Design Automation, 1999

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Interconnect Delay Estimation Models for Synthesis and Design Planning.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Relaxed Simulated Tempering for VLSI Floorplan Designs.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Bounded-skew clock and Steiner routing.

[BibT_eX]

[DOI]

Chung-Wen Albert Tsao

ACM Trans. Design Autom. Electr. Syst., 1998

An efficient algorithm for performance-optimal FPGA technology mapping with retiming.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

An efficient technique for device and interconnect optimization in deep submicron designs.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Physical Design, 1998

Intellectual property protection by watermarking combinational logic synthesis solutions.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Multiway partitioning with pairwise movement.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

How will CAD handle billion-transistor systems? (panel).

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Technology Mapping for FPGAs with Embedded Memory Blocks.

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Performance-driven routing with multiple sources.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Performance driven global routing for standard cell design.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

Interconnect design for deep submicron ICs.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Interconnect layout optimization under higher-order RLC model.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Global interconnect sizing and spacing with consideration of coupling capacitance.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.

[BibT_eX]

[DOI]

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.

[BibT_eX]

[DOI]

John Peck

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Optimal wiresizing for interconnects with multiple sources.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Combinational logic synthesis for LUT based field programmable gate arrays.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Multiway VLSI circuit partitioning based on dual net representation.

[BibT_eX]

[DOI]

Wilburt Labio

Narayanan Shivakumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Performance optimization of VLSI interconnect layout.

[BibT_eX]

[DOI]

Integr., 1996

Simultaneous buffer and wire sizing for performance and power optimization.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Buffered Steiner tree construction with wire sizing for interconnect layout optimization.

[BibT_eX]

[DOI]

Takumi Okamoto

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

An efficient approach to simultaneous transistor and interconnect sizing.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

RASP: A General Logic Synthesis System for SRAM-Based FPGAs.

[BibT_eX]

[DOI]

John Peck

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

An efficient multilayer MCM router based on four-via routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimal wiresizing under Elmore delay model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

The Supercomputer Supernet: A Scalable Distributed Terabit Network.

[BibT_eX]

[DOI]

J. High Speed Networks, 1995

Performance Driven Routing with Mulitiple Sources.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Minimum-Cost Bounded-Skew Clock Routing.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Bounded-skew clock and Steiner routing under Elmore delay.

[BibT_eX]

[DOI]

Chung-Wen Albert Tsao

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Exploitation signal flow and logic dependency in standard cell placement.

[BibT_eX]

[DOI]

Dongmin Xu

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

On the Minimum Density Interconnection Tree Problem.

[BibT_eX]

[DOI]

VLSI Design, 1994

Channel Density Minimization by Pin Permutation.

[BibT_eX]

[DOI]

Yang Cai

D. F. Wong

VLSI Design, 1994

Simultaneous driver and wire sizing for performance and power optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

On area/depth trade-off in LUT-based FPGA technology mapping.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On nominal delay minimization in LUT-based FPGA technology mapping.

[BibT_eX]

[DOI]

Integr., 1994

LUT-based FPGA technology mapping under arbitrary net-delay models.

[BibT_eX]

[DOI]

Comput. Graph., 1994

Parallel logic level simulation of VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th conference on Winter simulation, 1994

Multi-way VLSI circuit partitioning based on dual net representation.

[BibT_eX]

[DOI]

Wilburt Labio

Narayanan Shivakumar

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Acyclic Multi-Way Partitioning of Boolean Networks.

[BibT_eX]

[DOI]

Zheng Li

Rajive L. Bagrodia

Proceedings of the 31st Conference on Design Automation, 1994

1993

Physical models and efficient algorithms for over-the-cell routing in standard cell design.

[BibT_eX]

[DOI]

Bryan Preas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Matching-based methods for high-performance clock routing.

[BibT_eX]

[DOI]

Gabriel Robins

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A provably good multilayer topological planar routing algorithm in IC layout designs.

[BibT_eX]

[DOI]

Moazzem Hossain

Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A Provably Good Algorithm for <i>k</i>-Layer Topological Planar Routing Problems.

[BibT_eX]

[DOI]

Moazzem Hossain

Naveed A. Sherwani

Proceedings of the Sixth International Conference on VLSI Design, 1993

A Two-pole Circuit Model for VLSI High-speed Interconnection.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimum Density Interconneciton Trees.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Optimal wiresizing under the distributed Elmore delay model.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design.

[BibT_eX]

[DOI]

M'Lissa Smith

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Performance-Driven Interconnect Design Based on Distributed RC Delay Model.

[BibT_eX]

[DOI]

Dian Zhou

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Provably good performance-driven global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A new algorithm for standard cell global routing.

[BibT_eX]

[DOI]

Bryan Preas

Integr., 1992

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1992

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A fast multilayer general area router for MCM designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Maximal reduction of lookup-table based FPGAs.

[BibT_eX]

[DOI]

Kuang-Chien Chen

Proceedings of the conference on European design automation, 1992

Net Partitions Yield Better Module Partitions.

[BibT_eX]

[DOI]

Lars W. Hagen

Proceedings of the 29th Design Automation Conference, 1992

1991

A layout modification approach to via minimization.

[BibT_eX]

[DOI]

Khe-Sing The

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

On the k-layer planar subset and topological via minimization problems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Pin assignment with global routing for general cell designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Performance-Driven Global Routing for Cell Based ICs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

High-Performance Clock Routing Based on Recursive Geometric Aatching.

[BibT_eX]

[DOI]

Gabriel Robins

Proceedings of the 28th Design Automation Conference, 1991

1990

Over-the-cell channel routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

On the k-layer planar subset and via minimization problems.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.

[BibT_eX]

[DOI]

Bryan Preas

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Constrained floorplan design for flexible blocks.

[BibT_eX]

[DOI]

Sai-keung Dong

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Pin assignment with global routing.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

VIA Minimization by Layout Modification.

[BibT_eX]

[DOI]

Khe-Sing The

D. F. Wong

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A new approach to three- or four-layer channel routing.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A new formulation of yield enhancement problems for reconfigurable chips.

[BibT_eX]

[DOI]

Nany Hasan