Jason Baumgartner

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

2016

The art of semi-formal bug hunting.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2014

Scalable reachability analysis via automated dynamic netlist-based hint generation.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2014

Effective Liveness Verification Using a Transformation-Based Framework.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

Generalized counterexamples to liveness properties.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2013

GLA: gate-level abstraction revisited.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Fast cone-of-influence computation and estimation in problems with multiple properties.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Enhanced reachability analysis via automated dynamic netlist-based hint generation.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2012

IC3-guided abstraction.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2012

2011

Hybrid verification of a hardware modular reduction engine.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

Approximate reachability with combined symbolic and ternary simulation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

Optimal redundancy removal without fixedpoint computation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Coping with Moore's Law (and more): Supporting arrays in state-of-the-art model checkers.

[BibT_eX]

[DOI]

Michael L. Case

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009

Enhanced verification by temporal decomposition.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Scalable conditional equivalence checking: An automated invariant-generation based approach.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Speculative reduction-based scalable redundancy identification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Scalable liveness checking via property-preserving transformations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Invariant-Strengthened Elimination of Dependent State Elements.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Optimal Constraint-Preserving Netlist Simplification.

[BibT_eX]

[DOI]

Adnan Aziz

Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007

Formal verification of a pervasive interconnect bus system in a high-performance microprocessor.

[BibT_eX]

[DOI]

Thuyen Le

Tilman Glökler

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Semi-Formal Verification at IBM.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning.

[BibT_eX]

[DOI]

Barinjato Ramanandray

Paul Roessler

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2005

Functional formal verification on designs of pSeries microprocessors and communication subsystems.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2005

Scalable compositional minimization via static analysis.

[BibT_eX]

[DOI]

Fadi A. Zaraket

Adnan Aziz

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Automatic Formal Verification of Fused-Multiply-Add FPUs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Exploiting suspected redundancy without proving it.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Exploiting Constraints in Transformation-Based Verification.

[BibT_eX]

[DOI]

Adnan Aziz

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

Scalable Automated Verification via Expert-System Guided Transformations.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Enhanced Diameter Bounding via Structural.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

2002

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2002

Roget2000: a 2D hyperbolic tree visualization of Roget's Thesaurus.

[BibT_eX]

[DOI]

Tim A. Waugh

Proceedings of the Visualization and Data Analysis 2002, 2002

Property Checking via Structural Analysis.

[BibT_eX]

[DOI]

Jacob A. Abraham

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

Min-Area Retiming on Dynamic Circuit Structures.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Transformation-Based Verification Using Generalized Retiming.

[BibT_eX]

[DOI]